Datasheet ADL5202 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Wide Dynamic Range, High Speed, Digitally Controlled VGA |
| Pages / Page | 29 / 7 — Data Sheet. ADL5202. Pin No. Mnemonic. Description |
| Revision | D |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
Data Sheet. ADL5202. Pin No. Mnemonic. Description
Model Line for this Datasheet
Text Version of Document
Data Sheet ADL5202 Pin No. Mnemonic Description
15 VINB− Channel B Negative Input. 16 VINB+ Channel B Positive Input. 17 PWUPB Channel B Power-Up. A logic high (1.4 V ≤ PWUPB ≤ 3.3 V) enables Channel B. 19, 21 VOUTB− Channel B Negative Output. 20, 22 VOUTB+ Channel B Positive Output. 23, 24, 25, VPOS Positive Power Supply. 26, 27, 28 29, 31 VOUTA+ Channel A Positive Output. 30, 32 VOUTA− Channel A Negative Output. 34 PWUPA Channel A Power-Up. A logic high (1.4 V ≤ PWUPA ≤ 3.3 V) enables Channel A. 35 VINA+ Channel A Positive Input. 36 VINA− Channel A Negative Input. 37 LATCHA Channel A Latch. A logic low (0 V ≤ LATCHA ≤ 0.8 V) allows gain changes on Channel A. A logic high (1.4 V ≤ LATCHA ≤ 3.3 V) prevents gain changes on Channel A. 38 UPDN_DAT_A/A0 Data Pin for Channel A Up/Down Function (UPDN_DAT_A). Bit 0 for Channel A Parallel Gain Control Interface (A0). 39 UPDN_CLK_A/A1 Clock Interface for Channel A Up/Down Function (UPDN_CLK_A). Bit 1 for Channel A Parallel Gain Control Interface (A1). 40 FA_A/A2 Fast Attack (FA_A). In serial mode, a logic high (1.4 V ≤ FA_A ≤ 3.3 V) attenuates Channel A according to FA setting in the SPI word. Bit 2 for Channel A Parallel Gain Control Interface (A2). Rev. D | Page 7 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CHARACTERIZATION AND TEST CIRCUITS THEORY OF OPERATION DIGITAL INTERFACE OVERVIEW PARALLEL DIGITAL INTERFACE SERIAL PERIPHERAL INTERFACE (SPI) Fast Attack GAIN UP/DOWN INTERFACE TRUTH TABLE LOGIC TIMING CIRCUIT DESCRIPTION BASIC STRUCTURE Input System Output Amplifier Gain Control APPLICATIONS INFORMATION BASIC CONNECTIONS ADC DRIVING LAYOUT CONSIDERATIONS EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE EVALUATION BOARD SCHEMATICS AND ARTWORK EVALUATION BOARD CONFIGURATION OPTIONS Configuration Options for the Main Section Configuration Options for the USB Section OUTLINE DIMENSIONS ORDERING GUIDE
15 VINB− Channel B Negative Input. 16 VINB+ Channel B Positive Input. 17 PWUPB Channel B Power-Up. A logic high (1.4 V ≤ PWUPB ≤ 3.3 V) enables Channel B. 19, 21 VOUTB− Channel B Negative Output. 20, 22 VOUTB+ Channel B Positive Output. 23, 24, 25, VPOS Positive Power Supply. 26, 27, 28 29, 31 VOUTA+ Channel A Positive Output. 30, 32 VOUTA− Channel A Negative Output. 34 PWUPA Channel A Power-Up. A logic high (1.4 V ≤ PWUPA ≤ 3.3 V) enables Channel A. 35 VINA+ Channel A Positive Input. 36 VINA− Channel A Negative Input. 37 LATCHA Channel A Latch. A logic low (0 V ≤ LATCHA ≤ 0.8 V) allows gain changes on Channel A. A logic high (1.4 V ≤ LATCHA ≤ 3.3 V) prevents gain changes on Channel A. 38 UPDN_DAT_A/A0 Data Pin for Channel A Up/Down Function (UPDN_DAT_A). Bit 0 for Channel A Parallel Gain Control Interface (A0). 39 UPDN_CLK_A/A1 Clock Interface for Channel A Up/Down Function (UPDN_CLK_A). Bit 1 for Channel A Parallel Gain Control Interface (A1). 40 FA_A/A2 Fast Attack (FA_A). In serial mode, a logic high (1.4 V ≤ FA_A ≤ 3.3 V) attenuates Channel A according to FA setting in the SPI word. Bit 2 for Channel A Parallel Gain Control Interface (A2). Rev. D | Page 7 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CHARACTERIZATION AND TEST CIRCUITS THEORY OF OPERATION DIGITAL INTERFACE OVERVIEW PARALLEL DIGITAL INTERFACE SERIAL PERIPHERAL INTERFACE (SPI) Fast Attack GAIN UP/DOWN INTERFACE TRUTH TABLE LOGIC TIMING CIRCUIT DESCRIPTION BASIC STRUCTURE Input System Output Amplifier Gain Control APPLICATIONS INFORMATION BASIC CONNECTIONS ADC DRIVING LAYOUT CONSIDERATIONS EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE EVALUATION BOARD SCHEMATICS AND ARTWORK EVALUATION BOARD CONFIGURATION OPTIONS Configuration Options for the Main Section Configuration Options for the USB Section OUTLINE DIMENSIONS ORDERING GUIDE
