Datasheet LTM4680 (Analog Devices) - 103

LTM4680
PMBus COMMAND DETAILS Table 20. FAULTn Propagate Fault Configuration
The FAULT0 and FAULT1 pins are designed to provide electrical notification of selected events to the user. Some of these events are common to both output channels. Others are specific to an output channel. They can also be used to share faults between channels.
BIT(S) SYMBOL OPERATION
B[15] VOUT disabled while not decayed. This is used in a PolyPhase configuration when bit 0 of the MFR_CHAN_CONFIG_LTM4680 is a zero. If the channel is turned off, by toggling the RUN pin or commanding the part OFF, and then the RUN is reasserted or the part is commanded back on before the output has decayed, VOUT will not restart until the 12.5% decay is honored. The FAULT pin is asserted during this condition if bit 15 is asserted. B[14] Mfr_fault_propagate_short_CMD_cycle 0: No action 1: Asserts low if commanded off then on before the output has sequenced off. Re-asserts high tOFF(MIN) after sequence off. b[13] Mfr_fault_propagate_ton_max_fault 0: No action if a TON_MAX_FAULT fault is asserted 1: Associated output will be asserted low if a TON_MAX_FAULT fault is asserted FAULT0 is associated with page 0 TON_MAX_FAULT faults FAULT1 is associated with page 1 TON_MAX_FAULT faults b[12] Reserved b[11] Mfr_fault0_propagate_int_ot, 0: No action if the MFR_OT_FAULT_LIMIT fault is asserted Mfr_fault1_propagate_int_ot 1: Associated output will be asserted low if the MFR_OT_FAULT_LIMIT fault is asserted b[10] Reserved b[9] Reserved b[8] Mfr_fault0_propagate_ut, 0: No action if the UT_FAULT_LIMIT fault is asserted Mfr_fault1_propagate_ut 1: Associated output will be asserted low if the UT_FAULT_LIMIT fault is asserted FAULT0 is associated with page 0 UT faults FAULT1 is associated with page 1 UT faults b[7] Mfr_fault0_propagate_ot, 0: No action if the OT_FAULT_LIMIT fault is asserted Mfr_fault1_propagate_ot 1: Associated output will be asserted low if the OT_FAULT_LIMIT fault is asserted FAULT0 is associated with page 0 OT faults FAULT1 is associated with page 1 OT faults b[6] Reserved b[5] Reserved b[4] Mfr_fault0_propagate_input_ov, 0: No action if the VIN_OV_FAULT_LIMIT fault is asserted Mfr_fault1_propagate_input_ov 1: Associated output will be asserted low if the VIN_OV_FAULT_LIMIT fault is asserted b[3] Reserved b[2] Mfr_fault0_propagate_iout_oc, 0: No action if the IOUT_OC_FAULT_LIMIT fault is asserted Mfr_fault1_propagate_iout_oc 1: Associated output will be asserted low if the IOUT_OC_FAULT_LIMIT fault is asserted FAULT0 is associated with page 0 OC faults FAULT1 is associated with page 1 OC faults b[1] Mfr_fault0_propagate_vout_uv, 0: No action if the VOUT_UV_FAULT_LIMIT fault is asserted Mfr_fault1_propagate_vout_uv 1: Associated output will be asserted low if the VOUT_UV_FAULT_LIMIT fault is asserted FAULT0 is associated with page 0 UV faults FAULT1 is associated with page 1 UV faults b[0] Mfr_fault0_propagate_vout_ov, 0: No action if the VOUT_OV_FAULT_LIMIT fault is asserted Mfr_fault1_propagate_vout_ov 1: Associated output will be asserted low if the VOUT_OV_FAULT_LIMIT fault is asserted FAULT0 is associated with page 0 OV faults FAULT1 is associated with page 1 OV faults Rev. A For more information www.analog.com 103 Document Outline Features Applications Typical Application Description Table of Contents Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Simplified Block Diagram Decoupling Requirements Functional Diagram Test Circuits Operation Power Module Introduction Power Module Overview, Major Features EEPROM with ECC Power-Up and Initialization Soft-Start Time-Based Sequencing Voltage-Based Sequencing Shutdown Light-Load Current Operation Switching Frequency and Phase PWM Loop Compensation Output Voltage Sensing INTVCC/EXTVCC Power Output Current Sensing and Sub Milliohm DCR Current Sensing Input Current Sensing PolyPhase Load Sharing External/Internal Temperature Sense RCONFIG (Resistor Configuration) Pins Table 1. VOUTn_CFG Pin Strapping Look-Up Table for the LTM4680’s Output Voltage, Coarse Setting (Not Applicable if MFR_CONFIG_ALL[6] = 1b) Table 2. VTRIMn_CFG Pin Strapping Look-Up Table for the LTM4680’s Output Voltage, Fine Adjustment Setting (Not Applicable if MFR_CONFIG_ALL[6] = 1b) Table 3. FSWPH_CFG Pin Strapping Look-Up Table to Set the LTM4680’s Switching Frequency and Channel Phase-Interleaving Angle (Not Applicable if MFR_CONFIG_ALL[6] = 1b) Table 4. ASEL Pin Strapping Look-Up Table to Set the LTM4680’s Slave Address (Applicable Regardless of MFR_CONFIG_ALL[6] Setting) Table 5. LTM4680 MFR_ADDRESS Command Examples Expressed in 7- and 8-Bit Addressing Fault Detection and Handling Status Registers and ALERT Masking Figure 5. LTM4680 Status Register Summary Mapping Faults to FAULT Pins Power Good Pins CRC Protection Serial Interface Communication Protection Device Addressing Responses to VOUT and IIN/IOUT Faults Output Overvoltage Fault Response Output Undervoltage Response Peak Output Overcurrent Fault Response Responses to Timing Faults Responses to VIN OV Faults Responses to OT/UT Faults Internal Overtemperature Fault Response External Overtemperature and Undertemperature Fault Response Responses to Input Overcurrent and Output Undercurrent Faults Responses to External Faults Fault Logging Bus Timeout Protection Similarity Between PMBus, SMBus and I2C 2-Wire Interface PMBus Serial Digital Interface Table 6. Abbreviations of Supported Data Formats Figure 6. PMBus Timing Diagram Figures 7 to 24 PMBus Protocols PMBus Command Summary PMBus Commands Table 7. PMBus Commands Summary (Note: The Data Format Abbreviations Are Detailed in Table 8) Table 8. Data Format Abbreviations Applications Information VIN to VOUT Step-Down Ratios Input Capacitors Output Capacitors Light Load Current Operation Switching Frequency and Phase Output Current Limit Programming Minimum On-Time Considerations Variable Delay Time, Soft-Start and Output Voltage Ramping Digital Servo Mode Soft Off (Sequenced Off) Undervoltage Lockout Fault Detection and Handling Open-Drain Pins Phase-Locked Loop and Frequency Synchronization Input Current Sense Amplifier Programmable Loop Compensation Checking Transient Response PolyPhase Configuration Connecting The USB to I2C/SMBus/PMBus Controller to the LTM4680 In System LTpowerPlay: An Interactive GUI for Digital Power PMBus Communication and Command Processing Thermal Considerations and Output Current Derating Tables 10 thru 11: Output Current Derating Table 12. Channel Output Voltage vs Capacitor Selection, All Ceramic Configuration, 15A to 30A Load Step with 15A/µs Slew Rate Table 13. Channel Output Voltage vs Capacitor Selection, Bulk and Ceramic Cap Configuration, 15A to 30A Load Step with 15A/µs Slew Rate Table 14. Dual Phase Single Output Voltage vs Capacitor Selection, Bulk and Ceramic Cap Configuration, 30A to 60A Load Step with 30A/µs Slew Rate Derating Curves EMI Performance Safety Considerations Layout Checklist/Example Typical Applications PMBus Command Details Addressing and Write Protect General Configuration Commands On/Off/Margin PWM Configuration Voltage Input Voltage and Limits Output Voltage and Limits Output Current and Limits Input Current and Limits Temperature Power Stage DCR Temperature Calibration Timing Timing—On Sequence/Ramp Timing—Off Sequence/Ramp Precondition for Restart Fault Response Fault Responses All Faults Fault Responses Input Voltage Fault Responses Output Voltage Fault Responses Output Current Fault Responses IC Temperature Fault Responses External Temperature Fault Sharing Fault Sharing Propagation Fault Sharing Response Scratchpad Identification Fault Warning and Status Telemetry NVM Memory Commands Store/Restore Fault Logging Block Memory Write/Read Package Description Table 23. LTM4680 BGA Pinout Package Photograph Design Resources Related Parts