Datasheet InnoSwitch3-EP (Power Integrations) - 6

ManufacturerPower Integrations
DescriptionOff-Line CV/CC QR Flyback Switcher IC with Integrated Primary-Side Switch, Synchronous Rectification and FluxLink Feedback
Pages / Page34 / 6 — InnoSwitch3-EP. Minimum Off-Time. Maximum Switching Frequency. Frequency …
File Format / SizePDF / 3.5 Mb
Document LanguageEnglish

InnoSwitch3-EP. Minimum Off-Time. Maximum Switching Frequency. Frequency Soft-Start. Wait and Listen

InnoSwitch3-EP Minimum Off-Time Maximum Switching Frequency Frequency Soft-Start Wait and Listen

Model Line for this Datasheet

Text Version of Document

InnoSwitch3-EP
were requested. constant current regulation mode. The most likely event that could require an additional handshake is
Minimum Off-Time
when the primary stops switching as the result of a momentary line The secondary control er initiates a cycle request using the inductive- brown-out event. When the primary resumes operation, it will default connection to the primary. The maximum frequency of secondary- to a start-up condition and attempt to detect handshake pulses from cycle requests is limited by a minimum cycle off-time of t . This OFF(MIN) the secondary. is in order to ensure that there is sufficient reset time after primary conduction to deliver energy to the load. If the secondary does not detect that the primary responds to switching requests for 8 consecutive cycles, or if the secondary
Maximum Switching Frequency
detects that the primary is switching without cycle requests for 4 or The maximum switch-request frequency of the secondary control er more consecutive cycles, the secondary control er will initiate a is f . SREQ second handshake sequence. This provides additional protection
Frequency Soft-Start
against cross-conduction of the SR FET while the primary is At start-up the primary control er is limited to a maximum switching switching. This protection mode also prevents an output overvoltage frequency of f and 75% of the maximum programmed current limit condition in the event that the primary is reset while the secondary is SW at the switch-request frequency of 100 kHz. still in control. The secondary control er temporarily inhibits the FEEDBACK short
Wait and Listen
protection threshold (V ) until the end of the soft-start (t ) When the primary resumes switching after initial power-up recovery FB(OFF) SS(RAMP) time. After hand-shake is completed the secondary control er linearly from an input line voltage fault (UV or OV) or an auto-restart event, it ramps up the switching frequency from f to f over the t will assume control and require a successful handshake to relinquish SW SREQ SS(RAMP) time period. control to the secondary control er. In the event of a short-circuit or overload at start-up, the device will As an additional safety measure the primary will pause for an move directly into CC (constant-current) mode. The device will go auto-restart on-time period, t (~82 ms), before switching. During AR into auto-restart (AR), if the output voltage does not rise above the this “wait” time, the primary will “listen” for secondary requests. If it V threshold before the expiration of the soft-start timer (t ) sees two consecutive secondary requests, separated by ~30 ms, the FB(AR) SS(RAMP) after handshake has occurred. primary will infer secondary control and begin switching in slave mode. If no pulses occurs during the t “wait” period, the primary The secondary control er enables the FEEDBACK pin-short protection AR will begin switching under primary control until handshake pulses are mode (V ) at the end of the t time period. If the output FB(OFF) SS(RAMP) received. short maintains the FEEDBACK pin below the short-circuit threshold, the secondary will stop requesting pulses triggering an auto-restart
Audible Noise Reduction Engine
cycle. The InnoSwitch3-EP features an active audible noise reduction mode whereby the control er (via a “frequency skipping” mode of operation) If the output voltage reaches regulation within the t time SS(RAMP) avoids the resonant band (where the mechanical structure of the period, the frequency ramp is immediately aborted and the secondary power supply is most likely to resonate − increasing noise amplitude) control er is permitted to go full frequency. This will al ow the between 7 kHz and 12 kHz - 143 ms and 83 ms. If a secondary control er to maintain regulation in the event of a sudden transient control er switch request occurs within this time window from the last loading soon after regulation is achieved. The frequency ramp will conduction cycle, the gate drive to the power switch is inhibited. only be aborted if quasi-resonant-detection programming has already
Secondary Controller
occurred.
Maximum Secondary Inhibit Period
As shown in the block diagram in Figure 4, the IC is powered by a Secondary requests to initiate primary switching are inhibited to 4.4 V (V ) regulator which is supplied by either VOUT or FWD. The BPS maintain operation below maximum frequency and ensure minimum SECONDARY BYPASS pin is connected to an external decoupling off-time. Besides these constraints, secondary-cycle requests are capacitor and fed internal y from the regulator block. also inhibited during the “ON” time cycle of the primary switch (time The FORWARD pin also connects to the negative edge detection between the cycle request and detection of FORWARD pin falling block used for both handshaking and timing to turn on the SR FET edge). The maximum time-out in the event that a FORWARD pin connected to the SYNCHRONOUS RECTIFIER DRIVE pin. The falling edge is not detected after a cycle requested is ~30 ms. FORWARD pin voltage is used to determine when to turn off the
Output Voltage Protection
SR FET in discontinuous conduction mode operation. This is when In the event that the sensed voltage on the FEEDBACK pin is 2% the voltage across the R of the SR FET drops below zero volts. DS(ON) higher than the regulation threshold, a bleed current of ~2.5 mA (3 In continuous conduction mode (CCM) the SR FET is turned off when mA max) is applied on the OUTPUT VOLTAGE pin (weak bleed). This the feedback pulse is sent to the primary to demand the next bleed current increases to ~200 mA (strong bleed) in the event that switching cycle, providing excel ent synchronous operation, free of the FEEDBACK pin voltage is raised beyond ~10% of the internal any overlap for the FET turn-off. FEEDBACK pin reference voltage. The current sink on the OUTPUT VOLTAGE pin is intended to discharge the output voltage after The mid-point of an external resistor divider network between the momentary overshoot events. The secondary does not relinquish OUTPUT VOLTAGE and SECONDARY GROUND pins is tied to the control to the primary during this mode of operation. FEEDBACK pin to regulate the output voltage. The internal voltage comparator reference voltage is V (1.265 V). If the voltage on the FEEDBACK pin is sensed to be 20% higher than FB the regulation threshold, a command is sent to the primary to either The external current sense resistor connected between ISENSE and latch-off or begin an auto-restart sequence (see Secondary Fault SECONDARY GROUND pins is used to regulate the output current in Response in Feature Code Addendum). This integrated V OVP can OUT
6
Rev. G 07/19 www.power.com Document Outline Product Highlights Description Output Power Table Pin Functional Description InnoSwitch3-EP Functional Description Primary Controller Secondary Controller Applications Example Key Application Considerations Selection of Components Components for InnoSwitch3-EP Primary-Side Circuit Components for InnoSwitch3-EP Secondary-Side Circuit Recommendations for Circuit Board Layout Layout Example Quick Design Checklist Absolute Maximum Ratings Thermal Resistance Typical Performance Curves InSOP-24D Package Drawing InSOP-24D Package Marking Part Ordering Table MSL Table ESD and Latch-Up Table Part Ordering Information