Datasheet RX65N, RX651 Groups (Renesas) - 5
| Manufacturer | Renesas |
| Description | 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 2-MB flash memory |
| Pages / Page | 246 / 5 — Table 1.1. Outline of Specifications (4/10). Classification. … |
| File Format / Size | PDF / 2.8 Mb |
| Document Language | English |
Table 1.1. Outline of Specifications (4/10). Classification. Module/Function. Description
Model Line for this Datasheet
Text Version of Document
RX65N Group, RX651 Group 1. Overview
Table 1.1 Outline of Specifications (4/10) Classification Module/Function Description
I/O ports Programmable I/O ports I/O ports for the 177-pin TFLGA, 176-pin LFBGA, and 176-pin LFQFP I/O pins: 136 Input pin: 1 Pull-up resistors: 136 Open-drain outputs: 136 5-V tolerance: 19 I/O ports for the 145-pin TFLGA and 144-pin LFQFP I/O pins: 111 Input pin: 1 Pull-up resistors: 111 Open-drain outputs: 111 5-V tolerance: 18 I/O ports for the 100-pin TFLGA and 100-pin LFQFP I/O pins: 78 Input pin: 1 Pull-up resistors: 78 Open-drain outputs: 78 5-V tolerance: 17 I/O ports for the 64-pin TFBGA I/O pins: 41 Input pin: 1 Pull-up resistors: 41 Open-drain outputs: 41 5-V tolerance: 8 I/O ports for the 64-pin LFQFP I/O pins: 42 Input pin: 1 Pull-up resistors: 42 Open-drain outputs: 42 5-V tolerance: 8 Event link controller (ELC) Event signals such as interrupt request signals can be interlinked with the operation of functions such as timer counting, eliminating the need for intervention by the CPU to control the functions. 83 internal event signals can be freely combined for interlinked operation with connected functions. Event signals from peripheral modules can be used to change the states of output pins (of ports B and E). Changes in the states of pins (of ports B and E) being used as inputs can be interlinked with the operation of peripheral modules. R01DS0276EJ0230 Rev.2.30 Page 5 of 246 Jun 20, 2019 Document Outline Features 1. Overview 1.1 Outline of Specifications 1.2 List of Products 1.3 Block Diagram 1.4 Pin Functions 1.5 Pin Assignments 2. CPU 2.1 General-Purpose Registers (R0 to R15) 2.2 Control Registers 2.3 Accumulator 3. Address Space 3.1 Address Space 3.2 External Address Space 4. I/O Registers 4.1 I/O Register Addresses (Address Order) 5. Electrical Characteristics 5.1 Absolute Maximum Ratings 5.2 DC Characteristics 5.3 AC Characteristics 5.3.1 Reset Timing 5.3.2 Clock Timing 5.3.3 Timing of Recovery from Low Power Consumption Modes 5.3.4 Control Signal Timing 5.3.5 Bus Timing 5.3.6 EXDMAC Timing 5.3.7 Timing of On-Chip Peripheral Modules 5.4 USB Characteristics 5.5 A/D Conversion Characteristics 5.6 D/A Conversion Characteristics 5.7 Temperature Sensor Characteristics 5.8 Power-on Reset Circuit and Voltage Detection Circuit Characteristics 5.9 Oscillation Stop Detection Timing 5.10 Battery Backup Function Characteristics 5.11 Flash Memory Characteristics 5.12 Boundary Scan Appendix 1. Package Dimensions REVISION HISTORY General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products Notice
Table 1.1 Outline of Specifications (4/10) Classification Module/Function Description
I/O ports Programmable I/O ports I/O ports for the 177-pin TFLGA, 176-pin LFBGA, and 176-pin LFQFP I/O pins: 136 Input pin: 1 Pull-up resistors: 136 Open-drain outputs: 136 5-V tolerance: 19 I/O ports for the 145-pin TFLGA and 144-pin LFQFP I/O pins: 111 Input pin: 1 Pull-up resistors: 111 Open-drain outputs: 111 5-V tolerance: 18 I/O ports for the 100-pin TFLGA and 100-pin LFQFP I/O pins: 78 Input pin: 1 Pull-up resistors: 78 Open-drain outputs: 78 5-V tolerance: 17 I/O ports for the 64-pin TFBGA I/O pins: 41 Input pin: 1 Pull-up resistors: 41 Open-drain outputs: 41 5-V tolerance: 8 I/O ports for the 64-pin LFQFP I/O pins: 42 Input pin: 1 Pull-up resistors: 42 Open-drain outputs: 42 5-V tolerance: 8 Event link controller (ELC) Event signals such as interrupt request signals can be interlinked with the operation of functions such as timer counting, eliminating the need for intervention by the CPU to control the functions. 83 internal event signals can be freely combined for interlinked operation with connected functions. Event signals from peripheral modules can be used to change the states of output pins (of ports B and E). Changes in the states of pins (of ports B and E) being used as inputs can be interlinked with the operation of peripheral modules. R01DS0276EJ0230 Rev.2.30 Page 5 of 246 Jun 20, 2019 Document Outline Features 1. Overview 1.1 Outline of Specifications 1.2 List of Products 1.3 Block Diagram 1.4 Pin Functions 1.5 Pin Assignments 2. CPU 2.1 General-Purpose Registers (R0 to R15) 2.2 Control Registers 2.3 Accumulator 3. Address Space 3.1 Address Space 3.2 External Address Space 4. I/O Registers 4.1 I/O Register Addresses (Address Order) 5. Electrical Characteristics 5.1 Absolute Maximum Ratings 5.2 DC Characteristics 5.3 AC Characteristics 5.3.1 Reset Timing 5.3.2 Clock Timing 5.3.3 Timing of Recovery from Low Power Consumption Modes 5.3.4 Control Signal Timing 5.3.5 Bus Timing 5.3.6 EXDMAC Timing 5.3.7 Timing of On-Chip Peripheral Modules 5.4 USB Characteristics 5.5 A/D Conversion Characteristics 5.6 D/A Conversion Characteristics 5.7 Temperature Sensor Characteristics 5.8 Power-on Reset Circuit and Voltage Detection Circuit Characteristics 5.9 Oscillation Stop Detection Timing 5.10 Battery Backup Function Characteristics 5.11 Flash Memory Characteristics 5.12 Boundary Scan Appendix 1. Package Dimensions REVISION HISTORY General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products Notice
