Datasheet 5L2503 (IDT) - 3
| Manufacturer | IDT |
| Description | MicroClock Programmable Clock Generator |
| Pages / Page | 29 / 3 — Power Group Table 2. Power Group. Power Supply. DIV. MUX. PLL. DCO. XTAL |
| Revision | 20171024 |
| File Format / Size | PDF / 437 Kb |
| Document Language | English |
Power Group Table 2. Power Group. Power Supply. DIV. MUX. PLL. DCO. XTAL
Model Line for this Datasheet
Text Version of Document
5L2503 Datasheet
Power Group Table 2. Power Group Power Supply SE DIV MUX PLL DCO XTAL
VDDO OUT2/OUT3 V VDD1_8 OUT1 V V V V
Output Source Selection Register Settings Table 3. OUT3 Source OUT3 Source B35b7 B35b6
Divider 3 (DIV3) 0 0 Divider 5 (DIV5) 0 1 Divider 1 (DIV1) 1 0 32.768kHz DCO 1 1
Table 4. OUT2 Source OUT2 Source B35b5 B35b4
Divider 3 (DIV3) 0 0 Divider 5 (DIV5) 0 1 Divider 1 (DIV1) 1 0 32.768kHz DCO 1 1
Table 5. OUT1 Source OUT1 source B35b3 B35b2
Divider 3 (DIV3) 0 0 Divider 5 (DIV5) 0 1 Divider 1 (DIV1) 1 0 32.768kHz DCO 1 1
Table 6. DIV1 Source DIV1 source B35b1 B35b0
PLL1 0 0 DIV4 seed 1 X ©2017 Integrated Device Technology, Inc. 3 October 24, 2017 Document Outline Description Typical Applications Features Output Features Key Specifications Block Diagram Pin Assignments Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN – Top View Pin Descriptions Table 1. Pin Descriptions Power Group Table 2. Power Group Output Source Selection Register Settings Table 3. OUT3 Source Table 4. OUT2 Source Table 5. OUT1 Source Table 6. DIV1 Source Device Features and Functions DFC – Dynamic Frequency Control Figure 2. DFC Function Block Diagram Table 7. DFC Function Priority DFC Function Programming PPS – Proactive Power Saving Function Figure 3. PPS Function Block Diagram Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming Input Pin Function Table 8. OE1 Pin Function Table 9. SDA/SCL Function Spread Spectrum ORT – VCO Overshoot Reduction Technology PLL Features and Descriptions Table 10. Output Divider 1 Table 11. Output Dividers 2, 3, and 5 Table 12. Output Divider 4 Output Clock Test Conditions Absolute Maximum Ratings Table 13: Absolute Maximum Ratings Recommended Operating Conditions Table 14: Recommended Operating Conditions Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance (TA = +25 °C) Table 15: Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Recommended Crystal Characteristics Table 16: Crystal Characteristics DC Electrical Characteristics Table 17: DC Electrical Characteristics DC Electrical Characteristics for 1.8V LVCMOS Table 18: DC Electrical Characteristics for 1.8V LVCMOS AC Electrical Characteristics Table 19. AC Electrical Characteristics I2C Bus Characteristics Table 20. I2C Bus DC Characteristics Table 21. I2C Bus AC Characteristics Spread Spectrum Generation Specifications Table 22: Spread Spectrum Generation Specifications General I2C Serial Interface Information Package Drawings Figure 5. NVG12, 2.5 × 2.5 mm 12-DFN Package Drawing – Page 1 Figure 6. NVG12, 2.5 × 2.5 mm 12-DFN Package Drawing – Page 2 Marking Diagram Ordering Information Revision History
Power Group Table 2. Power Group Power Supply SE DIV MUX PLL DCO XTAL
VDDO OUT2/OUT3 V VDD1_8 OUT1 V V V V
Output Source Selection Register Settings Table 3. OUT3 Source OUT3 Source B35b7 B35b6
Divider 3 (DIV3) 0 0 Divider 5 (DIV5) 0 1 Divider 1 (DIV1) 1 0 32.768kHz DCO 1 1
Table 4. OUT2 Source OUT2 Source B35b5 B35b4
Divider 3 (DIV3) 0 0 Divider 5 (DIV5) 0 1 Divider 1 (DIV1) 1 0 32.768kHz DCO 1 1
Table 5. OUT1 Source OUT1 source B35b3 B35b2
Divider 3 (DIV3) 0 0 Divider 5 (DIV5) 0 1 Divider 1 (DIV1) 1 0 32.768kHz DCO 1 1
Table 6. DIV1 Source DIV1 source B35b1 B35b0
PLL1 0 0 DIV4 seed 1 X ©2017 Integrated Device Technology, Inc. 3 October 24, 2017 Document Outline Description Typical Applications Features Output Features Key Specifications Block Diagram Pin Assignments Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN – Top View Pin Descriptions Table 1. Pin Descriptions Power Group Table 2. Power Group Output Source Selection Register Settings Table 3. OUT3 Source Table 4. OUT2 Source Table 5. OUT1 Source Table 6. DIV1 Source Device Features and Functions DFC – Dynamic Frequency Control Figure 2. DFC Function Block Diagram Table 7. DFC Function Priority DFC Function Programming PPS – Proactive Power Saving Function Figure 3. PPS Function Block Diagram Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming Input Pin Function Table 8. OE1 Pin Function Table 9. SDA/SCL Function Spread Spectrum ORT – VCO Overshoot Reduction Technology PLL Features and Descriptions Table 10. Output Divider 1 Table 11. Output Dividers 2, 3, and 5 Table 12. Output Divider 4 Output Clock Test Conditions Absolute Maximum Ratings Table 13: Absolute Maximum Ratings Recommended Operating Conditions Table 14: Recommended Operating Conditions Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance (TA = +25 °C) Table 15: Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Recommended Crystal Characteristics Table 16: Crystal Characteristics DC Electrical Characteristics Table 17: DC Electrical Characteristics DC Electrical Characteristics for 1.8V LVCMOS Table 18: DC Electrical Characteristics for 1.8V LVCMOS AC Electrical Characteristics Table 19. AC Electrical Characteristics I2C Bus Characteristics Table 20. I2C Bus DC Characteristics Table 21. I2C Bus AC Characteristics Spread Spectrum Generation Specifications Table 22: Spread Spectrum Generation Specifications General I2C Serial Interface Information Package Drawings Figure 5. NVG12, 2.5 × 2.5 mm 12-DFN Package Drawing – Page 1 Figure 6. NVG12, 2.5 × 2.5 mm 12-DFN Package Drawing – Page 2 Marking Diagram Ordering Information Revision History
