Datasheet 5L2503 (IDT) - 6

5L2503 Datasheet
Input Pin Function
The input pins in 5L2503 have multiple functions. The OE1 pin can be configured as output enable control (OE) or chip power-down control (PD#) or Proactive Power Saving function (PPS). Furthermore, the OE1 pin can be configured as a single or two-pin Dynamic Frequency Control (DFC). SCL/SDA are also multiple function pins. The two pins can be configured as output enable control (OE), or I2C interface or Dynamic Frequency Control (DFC) functions by programming and hardware pin latch.
Table 8. OE1 Pin Function Byte30 Function bit6 bit5
OUT1 output enable/disable 0 0 Global Power Down (PD#) 0 1 OUT1 Proactive Power Saving Input (OUT1 PPS) 1 0 DFC0 1 1
Table 9. SDA/SCL Function SEL_DFC (latched) Enable OE2/3 B36<2> DFC_EN B32<4> OE1 Funsel B30<6:5> Function of SCL/SDA
0 0 0 00, 01, 10 N/A 0 0 1 00, 01, 10 SCL = DFC1, SDA = DFC0 0 1 X 00, 01, 10 SCL = OE3, SDA = OE2 1 X X 00, 01, 10 SCL, SDA
Spread Spectrum
The 5L2503 supports spread spectrum clocks from PLL1. PLL1 has built-in analog spread spectrum; PLL2 and PLL3 use seed clock from PLL1.
ORT – VCO Overshoot Reduction Technology
The 5L2503 supports innovate the VCO overshoot reduction technology to prevent the output clock frequency spike when the device is change frequency on the fly or doing DFC (Dynamic Frequency Control) function. The VCO frequency change are under control instead of freerun to targeted frequency.
PLL Features and Descriptions Table 10. Output Divider 1 Output Divider Bits <3:2> Output Divider Bits <1:0> 00 01 10 11
00 1 2 4 8 01 4 8 16 32 10 5 10 20 40 11 6 12 24 48 ©2017 Integrated Device Technology, Inc. 6 October 24, 2017 Document Outline Description Typical Applications Features Output Features Key Specifications Block Diagram Pin Assignments Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN – Top View Pin Descriptions Table 1. Pin Descriptions Power Group Table 2. Power Group Output Source Selection Register Settings Table 3. OUT3 Source Table 4. OUT2 Source Table 5. OUT1 Source Table 6. DIV1 Source Device Features and Functions DFC – Dynamic Frequency Control Figure 2. DFC Function Block Diagram Table 7. DFC Function Priority DFC Function Programming PPS – Proactive Power Saving Function Figure 3. PPS Function Block Diagram Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming Input Pin Function Table 8. OE1 Pin Function Table 9. SDA/SCL Function Spread Spectrum ORT – VCO Overshoot Reduction Technology PLL Features and Descriptions Table 10. Output Divider 1 Table 11. Output Dividers 2, 3, and 5 Table 12. Output Divider 4 Output Clock Test Conditions Absolute Maximum Ratings Table 13: Absolute Maximum Ratings Recommended Operating Conditions Table 14: Recommended Operating Conditions Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance (TA = +25 °C) Table 15: Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Recommended Crystal Characteristics Table 16: Crystal Characteristics DC Electrical Characteristics Table 17: DC Electrical Characteristics DC Electrical Characteristics for 1.8V LVCMOS Table 18: DC Electrical Characteristics for 1.8V LVCMOS AC Electrical Characteristics Table 19. AC Electrical Characteristics I2C Bus Characteristics Table 20. I2C Bus DC Characteristics Table 21. I2C Bus AC Characteristics Spread Spectrum Generation Specifications Table 22: Spread Spectrum Generation Specifications General I2C Serial Interface Information Package Drawings Figure 5. NVG12, 2.5 × 2.5 mm 12-DFN Package Drawing – Page 1 Figure 6. NVG12, 2.5 × 2.5 mm 12-DFN Package Drawing – Page 2 Marking Diagram Ordering Information Revision History