Datasheet ADP5072 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 1 A/0.6 A DC-to-DC Switching Regulator with Independent Positive and Negative Outputs |
| Pages / Page | 24 / 5 — Data Sheet. ADP5072. ABSOLUTE MAXIMUM RATINGS Table 3. THERMAL … |
| File Format / Size | PDF / 655 Kb |
| Document Language | English |
Data Sheet. ADP5072. ABSOLUTE MAXIMUM RATINGS Table 3. THERMAL RESISTANCE. Parameter. Rating. Table 4. Thermal Resistance
Model Line for this Datasheet
Text Version of Document
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Data Sheet ADP5072 ABSOLUTE MAXIMUM RATINGS Table 3. THERMAL RESISTANCE Parameter Rating
Thermal performance is directly linked to printed circuit board PVIN, AVIN −0.3 V to +6V (PCB) design and operating environment. Careful attention to SW1 −0.3 V to +40 V PCB thermal design is required. SW2 PVIN − 40 V to PVIN + 0.3 V θJA is the natural convection junction to ambient thermal PGND, AGND −0.3 V to +0.3 V resistance measured in a one cubic foot sealed enclosure. θJC is EN1, EN2, FB1, FB2, SYNC, −0.3 V to +6 V the junction to case thermal resistance. ψJT is the junction to COMP1, COMP2, SLEW, SS, −0.3 V to AVIN + 0.3 V case thermal characterization parameter. SEQ, VREF Operating Junction −40°C to +125°C
Table 4. Thermal Resistance
Temperature Range
Package Type θJA θJC ΨJT Unit
Storage Temperature Range −65°C to +150°C CB-20-141, 2 50 0.54 0.13 C/W Soldering Conditions JEDEC J-STD-020 1 Stresses at or above those listed under Absolute Maximum θJA and ΨJT are based on a 4-layer printed circuit board (PCB) (two signal and two power planes) with nine thermal vias connecting the exposed pad to the Ratings may cause permanent damage to the product. This is a ground plane as recommended in the Layout Considerations section. θJC is stress rating only; functional operation of the product at these measured at the top of the package and is independent of the PCB. The ΨJT value is more appropriate for calculating junction to case temperature in the or any other conditions above those indicated in the operational application. section of this specification is not implied. Operation beyond 2 The thermal resistance values specified in Table 4 are simulated based on JEDEC specifications, unless specified otherwise, and must be used in the maximum operating conditions for extended periods may compliance with JESD51-12. affect product reliability.
ESD CAUTION
Rev. 0 | Page 5 of 24 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PWM MODE PSM MODE UNDERVOLTAGE LOCKOUT (UVLO) OSCILLATOR AND SYNCHRONIZATION INTERNAL REGULATOR PRECISION ENABLING SOFT START SLEW RATE CONTROL CURRENT-LIMIT PROTECTION OVERVOLTAGE PROTECTION THERMAL SHUTDOWN START-UP SEQUENCE APPLICATIONS INFORMATION COMPONENT SELECTION Feedback Resistors OUTPUT CAPACITORS Input Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator LOOP COMPENSATION Boost Regulator Inverting Regulator COMMON APPLICATIONS LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADP5072 ABSOLUTE MAXIMUM RATINGS Table 3. THERMAL RESISTANCE Parameter Rating
Thermal performance is directly linked to printed circuit board PVIN, AVIN −0.3 V to +6V (PCB) design and operating environment. Careful attention to SW1 −0.3 V to +40 V PCB thermal design is required. SW2 PVIN − 40 V to PVIN + 0.3 V θJA is the natural convection junction to ambient thermal PGND, AGND −0.3 V to +0.3 V resistance measured in a one cubic foot sealed enclosure. θJC is EN1, EN2, FB1, FB2, SYNC, −0.3 V to +6 V the junction to case thermal resistance. ψJT is the junction to COMP1, COMP2, SLEW, SS, −0.3 V to AVIN + 0.3 V case thermal characterization parameter. SEQ, VREF Operating Junction −40°C to +125°C
Table 4. Thermal Resistance
Temperature Range
Package Type θJA θJC ΨJT Unit
Storage Temperature Range −65°C to +150°C CB-20-141, 2 50 0.54 0.13 C/W Soldering Conditions JEDEC J-STD-020 1 Stresses at or above those listed under Absolute Maximum θJA and ΨJT are based on a 4-layer printed circuit board (PCB) (two signal and two power planes) with nine thermal vias connecting the exposed pad to the Ratings may cause permanent damage to the product. This is a ground plane as recommended in the Layout Considerations section. θJC is stress rating only; functional operation of the product at these measured at the top of the package and is independent of the PCB. The ΨJT value is more appropriate for calculating junction to case temperature in the or any other conditions above those indicated in the operational application. section of this specification is not implied. Operation beyond 2 The thermal resistance values specified in Table 4 are simulated based on JEDEC specifications, unless specified otherwise, and must be used in the maximum operating conditions for extended periods may compliance with JESD51-12. affect product reliability.
ESD CAUTION
Rev. 0 | Page 5 of 24 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PWM MODE PSM MODE UNDERVOLTAGE LOCKOUT (UVLO) OSCILLATOR AND SYNCHRONIZATION INTERNAL REGULATOR PRECISION ENABLING SOFT START SLEW RATE CONTROL CURRENT-LIMIT PROTECTION OVERVOLTAGE PROTECTION THERMAL SHUTDOWN START-UP SEQUENCE APPLICATIONS INFORMATION COMPONENT SELECTION Feedback Resistors OUTPUT CAPACITORS Input Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator LOOP COMPENSATION Boost Regulator Inverting Regulator COMMON APPLICATIONS LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE
