Datasheet LTM4651 (Analog Devices) - 8

LTM4651
PIN FUNCTIONS PACKAGE ROW AND COLUMN LABELING MAY VARY RUN (F4):
Run Control Pin. A voltage above 1.2V (with
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
respect to GND) commands the module to regulate its
LAYOUT CAREFULLY.
output voltage. Undervoltage lockout (UVLO) can be
VIN (A1 – A3, B3):
Power Input Pins. Apply input voltage implemented by connecting RUN to the midpoint node and input decoupling capacitance directly between VIN formed by a resistor-divider between VIN and GND. RUN and a power ground (PGND) plane. features 130mV of hysteresis. See the Applications In-
V
formation section.
D (A4, B4, C4):
Drain of the Converter’s Primary Switching MOSFET. Apply at least one 4.7μF high frequency ceramic
INTVCC (G3):
Internal Regulator, 3.3V Output with Re- decoupling capacitor directly from V – D to VOUT . Give this spect to V – OUT . Internal control circuits and MOSFET- capacitor higher layout priority (closer proximity to the drivers derive power from INTVCC bias. When operating module) than any VIN decoupling capacitors. 3.6V < SVIN ≤ 58V, an LDO generates INTVCC from SVIN
SV
when RUN is logic high (RUN >1.2V). No external decoupling
IN (C3):
Input Voltage Supply for Small-Signal Circuits. SV is required. When RUN is logic low (RUN – GND < 1.2V), IN is the input to the INTVCC LDO. Connect SVIN directly to V the INTV IN. No decoupling capacitor is needed on this pin. CC LDO is off, i.e., INTVCC is unregulated. (Also see EXTV
V –
CC.) It is not recommended to load INTVCC with
OUT (A5, B5, C2, C5, D5, E5, F5, G4 – 5, H3, H5,
external circuits exceeding ~10mA. See the Applications
J3 – 5, K4 – 5, L4 – 5):
Negative Power Output of the Information section and Note 8. LTM4651. Connect all V – OUT pins to the application’s V –
EXTV
OUT plane. Apply the output filter capacitor and the
CC (F3):
External Bias, Auxiliary Input to the INTVCC output load between these and the PGND pins. Regulator. When EXTV – CC – VOUT exceeds 3.2V and SV – exceeds 5V, the INTV
PGND (K1 – 3, L1 – 3):
Power Ground Pins of the LTM4651. IN – VOUT CC LDO derives power from EXTV Electrically connect all pins to the application’s PGND plane. CC bias instead of the SVIN path. This technique can reduce LDO losses considerably, resulting in a cor-
GND (D4):
Ground Reference for RUN, CLKIN, and PGOOD responding reduction in module junction temperature. For Signals. Connect GND directly to the PGND power ground applications where |V – OUT | > 4V, realize this benefit by plane. connecting EXTVCC to PGND through a resistor. (See the
GND
Application Information section for resistor value.) When
SNS (G1, H1):
Voltage Sense, PGND Input and Feed- back Signal. Connect GND taking advantage of this EXTVCC feature, locally decouple SNS to PGND at the point of – load (POL). Pins G1 and H1 are electronically connected EXTVCC to VOUT with a 1µF ceramic capacitor—otherwise, to each other internal to the module, and thus it is only leave EXTVCC open circuit. necessary to connect one GNDSNS pin to PGND at the POL.
ISETb (F1):
1.5nF Soft-Start Capacitor. Connect ISETb The remaining GNDSNS pin can be used for redundant con- to ISETa to achieve default soft-start characteristics, if nectivity or routed to an ICT test point for design-for-test desired—otherwise, leave ISETb open circuit. See ISETa. considerations, as desired.
ISETa (F2):
Accurate 50µA Current Source. Positive input
SV –
–
OUT (E4, G2, H2):
Voltage Sense, VOUT Input. Connect to the error amplifier. Connect a resistor (RSET) from this Pin H2 to V – – – OUT directly under the LTM4651. The SVOUT pin to SVOUT to program the desired LTM4651 output volt- pins at locations E4 and G2 are electrically connected age, V – OUT = –RSET • 50µA. A capacitor can be connected to each other internal to the module, and thus it is only from ISETa to SV – OUT to soft-start the output voltage and necessary to connect one SV – – OUT pin to VOUT under reduce start-up inrush current. Connect ISETa to ISETb in the module. The remaining SV – OUT pins can be used for order to achieve default soft-start, if desired. See ISETb. redundant connectivity or routed to an ICT test point for design-for-test considerations, as desired. Rev. A 8 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Simplified Block Diagram Test Circuit Decoupling Requirements Operation Applications Information Typical Applications Package Photograph Package Description Typical Application Related Parts