Datasheet LT3462, LT3462A (Analog Devices) - 5

link to page 5 link to page 5 LT3462/LT3462A
BLOCK DIAGRAM
SW D – A1 DRIVER E AMP – FB + A2 R Q R COMP Q1 C + S DO CC LG SHUTDOWN + BIAS CURRENT CANCELLATION 0.1Ω ISRC OFF  3µA – ON  180µA RAMP GND SDREF GENERATOR SHUTDOWN VOUT VOUT 1.2MHz* OSCILLATOR R1 (EXTERNAL) CS1 (EXTERNAL) *LT3462A IS 2.7MHz FB SDREF – R2 (EXTERNAL) CS2 (EXTERNAL) Q2 SDREF 1.265V VIN + C REFERENCE S1, CS2 OPTIONAL SOFT-START COMPONENTS 3462 F01
Figure 1. Block Diagram OPERATION
The LT3462 uses a constant frequency, current mode of the PWM comparator. This current limit cell protects control scheme to provide excellent line and load regula‑ the power switch as well as various external components tion. Operation can be best understood by referring to the connected to the LT3462. Block Diagram in Figure 1. At the start of each oscillator SDREF is a dual function input pin. When driven low it cycle, the SR latch is set, turning on the power switch shuts the part down, reducing quiescent supply current Q1. A voltage proportional to the switch current is added to less than 10µA. When not driven low, the SDREF pin to a stabilizing ramp and the resulting sum is fed into has an internal pul ‑up current that turns the regulator on. the positive terminal of the PWM comparator. When this Once the part is enabled, the SDREF pin sources up to voltage exceeds the voltage at the output of the EAMP, the 180µA nominally at a fixed voltage of 1.265V through SR latch is reset, turning off the power switch. The level external resistor R2 to FB. If there is no fault condition at the output of the EAMP is simply an amplified version present, FB will regulate to 0V, and V of the difference between the feedback voltage and GND. OUT will regulate to 1.265V • (–R1/R2). An optional soft‑start circuit uses the In this manner, the error amplifier sets the correct peak fixed SDREF pull‑up current and a capacitor from SDREF current level to keep the output in regulation. If the error to V amplifier’s output increases, more current is taken from OUT to set the dV/dt on VOUT. In shutdown, an FB bias current cancellation circuit supplies up to 150µA biasing the output; if it decreases, less current is taken. One func‑ current to external resistor R1 while V tion not shown in Figure 1 is the current limit. The switch OUT is lower than FB. This function eliminates R2 loading of SDREF during current is constantly monitored and not allowed to exceed shutdown. As a result, supply current in shutdown may the nominal value of 400mA. If the switch current reaches exceed 10µA by the amount of current flowing in R1. 400mA, the SR latch is reset regardless of the output state Rev A For more information www.analog.com 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts