Datasheet ICM7555 (NXP) - 8
| Manufacturer | NXP |
| Description | General purpose CMOS timer |
| Pages / Page | 22 / 8 — NXP Semiconductors. ICM7555. General purpose CMOS timer. Fig 8. Minimum … |
| File Format / Size | PDF / 125 Kb |
| Document Language | English |
NXP Semiconductors. ICM7555. General purpose CMOS timer. Fig 8. Minimum pulse width for triggering. Fig 9
Model Line for this Datasheet
ICM7555
Text Version of Document
NXP Semiconductors ICM7555 General purpose CMOS timer
002aae410 500 TRIGGER pulse width (ns) VDD = 18 V 5 V 400 2 V 300 200 100 0 0 10 20 30 40 lowest voltage level of TRIGGER pulse (% VDD)
Fig 8. Minimum pulse width for triggering
002aae411 1000 tPD (ns) Tamb = −55 °C 750 +25 °C +125 °C 500 250 0 0 10 20 30 40 lowest voltage level of TRIGGER pulse (% VDD)
Fig 9. Propagation delay versus voltage level of TRIGGER pulse (VDD = 5 V)
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 8 of 22
Document Outline 1. General description 2. Features 3. Applications 4. Ordering information 5. Functional diagram 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description 7.1 Function selection 8. Limiting values 9. Characteristics 10. Typical performance curves 11. Application information 11.1 General 11.2 Power supply considerations 11.3 Output drive capability 11.4 Astable operation 11.5 Monostable operation 11.6 Control voltage 11.7 RESET 12. Package outline 13. Soldering of SMD packages 13.1 Introduction to soldering 13.2 Wave and reflow soldering 13.3 Wave soldering 13.4 Reflow soldering 14. Soldering of through-hole mount packages 14.1 Introduction to soldering through-hole mount packages 14.2 Soldering by dipping or by solder wave 14.3 Manual soldering 14.4 Package related soldering information 15. Abbreviations 16. Revision history 17. Legal information 17.1 Data sheet status 17.2 Definitions 17.3 Disclaimers 17.4 Trademarks 18. Contact information 19. Contents
002aae410 500 TRIGGER pulse width (ns) VDD = 18 V 5 V 400 2 V 300 200 100 0 0 10 20 30 40 lowest voltage level of TRIGGER pulse (% VDD)
Fig 8. Minimum pulse width for triggering
002aae411 1000 tPD (ns) Tamb = −55 °C 750 +25 °C +125 °C 500 250 0 0 10 20 30 40 lowest voltage level of TRIGGER pulse (% VDD)
Fig 9. Propagation delay versus voltage level of TRIGGER pulse (VDD = 5 V)
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 8 of 22
Document Outline 1. General description 2. Features 3. Applications 4. Ordering information 5. Functional diagram 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description 7.1 Function selection 8. Limiting values 9. Characteristics 10. Typical performance curves 11. Application information 11.1 General 11.2 Power supply considerations 11.3 Output drive capability 11.4 Astable operation 11.5 Monostable operation 11.6 Control voltage 11.7 RESET 12. Package outline 13. Soldering of SMD packages 13.1 Introduction to soldering 13.2 Wave and reflow soldering 13.3 Wave soldering 13.4 Reflow soldering 14. Soldering of through-hole mount packages 14.1 Introduction to soldering through-hole mount packages 14.2 Soldering by dipping or by solder wave 14.3 Manual soldering 14.4 Package related soldering information 15. Abbreviations 16. Revision history 17. Legal information 17.1 Data sheet status 17.2 Definitions 17.3 Disclaimers 17.4 Trademarks 18. Contact information 19. Contents
