Datasheet MAX16956 (Maxim) - 10

ManufacturerMaxim
Description36V, 300mA, Mini Buck Converter with 1.1µA IQ
Pages / Page16 / 10 — Detailed Description. DC-DC Converter Control Architecture. System Enable …
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Detailed Description. DC-DC Converter Control Architecture. System Enable (EN). Linear Regulator Output (BIAS)

Detailed Description DC-DC Converter Control Architecture System Enable (EN) Linear Regulator Output (BIAS)

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MAX16956 36V, 300mA, Mini Buck Converter with 1.1µA IQ
Detailed Description
providing current to the output. The output capacitor The MAX16956 is a small, current-mode buck converter stores charge when the inductor current exceeds the that features synchronous rectification and requires no required load current and discharges when the inductor external compensation network. The device operates current is lower, smoothing the voltage across the load. from a 3.5V to 36V supply voltage and can deliver up The device features load-line architecture to reduce the to 300mA output current. Frequency is fixed at 2.1MHz, output capacitance needed, potentially saving system which allows for small external components, reduced cost and size. The output voltage is positioned slightly output ripple, and guarantees no AM-band interference. positive at no load, still within the tolerance window, to take advantage of the fact that any load disturbance is The device offers fixed output voltages of 5V and 3.3V. a load step only. This increases the amount of margin The device also offers adjustable output-voltage versions available to the undershoot that occurs on a load step, that can be set between 1V and 10V by using an exter- allowing a reduction in the required output capacitance. nal resistive divider. Voltage quality can be monitored As the load increases, a small but controlled amount by observing the RESET signal. The device offers both of load regulation (“load-line”) error occurs, so that at forced-PWM and skip mode, with ultra-low-quiescent cur- heavier loads the voltage is positioned slightly below rent of 1.1µA in skip mode. nominal. This takes advantage of the fact that any load
DC-DC Converter Control Architecture
disturbance is load released, increasing the amount of margin available to the overshoot that occurs. The device step-down converter uses a PWM peak current- The device can operate in either forced-PWM or skip mode control scheme, with a load-line architecture. Peak mode. In forced-PWM mode, the converter maintains a current-mode control provides several advantages over constant switching frequency, regardless of load, to allow voltage-mode control, including precise control of the induc- for easier filtering of the switching noise. The device tor current on a cycle-by-cycle basis, simpler compensa- includes proprietary circuitry that dramatically reduces tion, and inherent compensation for line voltage variation. quiescent current consumption in skip mode, improving An internal transconductance amplifier establishes an light-load efficiency. See the Forced PWM/Skip Modes integrated error voltage. The heart of the PWM control- section for further details. ler is an open-loop comparator: one input is the inte-
System Enable (EN)
grated voltage-feedback signal; the other consists of the amplified current-sense signal plus slope-compensation An enable control input (EN) activates the device from its low-power shutdown mode. EN is compatible with inputs ramp. Integrated high-side current sensing is used, which from automotive battery level down to 3.5V. The high- reduces component count and layout risk by eliminating voltage compatibility allows EN to be connected to SUP, the need to carefully route sensitive external signals. KEY/KL30, or the inhibit pin (INH) of a CAN transceiver. Error-amplifier compensation is also integrated, once again simplifying the power-supply designer’s task while
Linear Regulator Output (BIAS)
eliminating external components. The device includes a 5V linear regulator output (BIAS) At each rising edge of the internal clock, the high-side that provides power to the internal circuit blocks. Connect MOSFET turns on until the PWM comparator trips, the a 1µF ceramic capacitor from BIAS to AGND. Do not load maximum duty cycle is reached, or the peak current limit this pin externally. is reached (see the Current Limit /Short-Circuit Protection
Undervoltage Lockout
section). During this on-time, current ramps up through the inductor, storing energy in a magnetic field and When VBIAS drops below the undervoltage-lockout sourcing current to the output. The current-mode feed- (UVLO) level of VUVLO = 2.8V (typ), the device assumes back system regulates the peak inductor current as a that the supply voltage is too low for proper operation, so function of the output-voltage error signal. During the the UVLO circuitry inhibits switching. When VBIAS rises second-half of the cycle, the high-side MOSFET turns above the UVLO rising threshold, the controller enters the off and the low-side MOSFET turns on. The inductor startup sequence and then resumes normal operation. releases the stored energy as the current ramps down, www.maximintegrated.com Maxim Integrated │ 10