Datasheet CMX7146 (CML Microcircuits) - 6
| Manufacturer | CML Microcircuits |
| Description | BPSK Wireless Data Modulator |
| Pages / Page | 37 / 6 — CMX7146. Signal. 48-lead. Type. Description. Name. No other electrical … |
| File Format / Size | PDF / 2.1 Mb |
| Document Language | English |
CMX7146. Signal. 48-lead. Type. Description. Name. No other electrical connection is permitted. Notes:
Model Line for this Datasheet
Text Version of Document
BPSK Wireless Data Modulator CMX7146
CMX7146 Signal 48-lead Type Description Q3 Name 29
AUXADC3 IP Auxiliary ADC input 3
30
AUXADC4 IP Auxiliary ADC input 4 Analog +3.3V supply rail. Levels and thresholds within the device
31
AVdd PWR are proportional to this voltage. This pin should be decoupled to AVss by capacitors mounted close to the device pins.
32
AUXDAC1 OP Auxiliary DAC output 1 / RAMDAC
33
AUXDAC2 OP Auxiliary DAC output 2
34
AVss PWR Analog Ground
35
AUXDAC3 OP Auxiliary DAC output 3
36
AUXDAC4 OP Auxiliary DAC output 4
37
DVss PWR Digital Ground Internally generated 2.5V supply voltage. Must be decoupled to DVss by capacitors mounted close to the device pins. No other
38
VDEC PWR connections allowed, except for the optional connection to RFVdd.
39
XTAL / CLOCK IP input from the external clock source or Xtal The output of the on-chip Xtal oscillator inverter. NC if external
40
XTALN OP Clock used. Digital +3.3V supply rail. This pin should be decoupled to DVss by
41
DVdd PWR capacitors mounted close to the device pins.
42
COMMAND DATA IP C-BUS: Serial data input from the µC C-BUS: A 3-state C-BUS serial data output to the µC. This output is
43
REPLY DATA TS OP high impedance when not sending data to the µC.
44
FSO BI SPI bus Chip Select
45
DVss PWR Digital Ground
46
SERIAL CLOCK IP C-BUS: The C-BUS serial clock input from the µC
47
SYSCLK2 OP Synthesized Digital System Clock Output 2
48
CSN IP C-BUS: The C-BUS chip select input from the µC On this device, the exposed central metal pad may be electrically EXPOSED unconnected or, alternatively, may be connected to Analogue METAL PAD SUBSTRATE ~ Ground (AVss).
No other electrical connection is permitted. Notes:
IP = Input (+ PU/PD = internal pullup / pulldown resistor) OP = Output BI = Bidirectional TS OP = 3-state Output PWR = Power Connection NC = No Connection - should NOT be connected to any signal. 2019 CML Microsystems Plc Page 6 D/7146/1 Document Outline Datasheet Front Page 1 Brief Description 1.1 History 2 Signal List 3 External Components 4 PCB Layout Guidelines and Power Supply Decoupling 5 General Description 5.1 CMX7146 Features 6 Detailed Descriptions 6.1 Xtal Frequency 6.2 Host Interface 6.2.1 C-BUS Operation 6.3 Function Image Loading 6.3.1 FI Loading from Host Controller 6.3.2 FI Loading from Flash/EEPROM 6.4 Device Control 6.4.1 Device Configuration (using the Programming Register) 6.4.2 Device Configuration (using dedicated registers) 6.4.3 Interrupt Operation 6.4.4 Signal Routing 6.4.5 Loading Transmit Data 6.4.6 The Transmit Sequence 6.4.7 Other Modem Modes 6.4.8 Data Transfer 6.4.9 Raw Data Transfer 6.4.10 Pre-loading transmit data 6.4.11 Auxiliary clock rates 6.4.12 Auxiliary data 6.4.13 GPIO Pin Operation 6.4.14 Auxiliary ADC Operation 6.4.15 Auxiliary DAC / RAMDAC Operation 6.5 Digital System Clock Generators 6.5.1 System Clock Operation 6.6 Signal Level Optimisation 6.7 C-BUS Register Summary 7 CMX7146 FI-1.x Features 7.1 Modulation 7.2 Radio Interface 7.3 Transmit Performance 8 Performance Specification 8.1 Electrical Performance 8.1.1 Absolute Maximum Ratings 8.1.2 Operating Limits 8.1.3 Operating Characteristics 8.1.4 Parametric Performance 8.2 C-BUS Timing 8.3 Packaging END OF DOCUMENT
CMX7146 Signal 48-lead Type Description Q3 Name 29
AUXADC3 IP Auxiliary ADC input 3
30
AUXADC4 IP Auxiliary ADC input 4 Analog +3.3V supply rail. Levels and thresholds within the device
31
AVdd PWR are proportional to this voltage. This pin should be decoupled to AVss by capacitors mounted close to the device pins.
32
AUXDAC1 OP Auxiliary DAC output 1 / RAMDAC
33
AUXDAC2 OP Auxiliary DAC output 2
34
AVss PWR Analog Ground
35
AUXDAC3 OP Auxiliary DAC output 3
36
AUXDAC4 OP Auxiliary DAC output 4
37
DVss PWR Digital Ground Internally generated 2.5V supply voltage. Must be decoupled to DVss by capacitors mounted close to the device pins. No other
38
VDEC PWR connections allowed, except for the optional connection to RFVdd.
39
XTAL / CLOCK IP input from the external clock source or Xtal The output of the on-chip Xtal oscillator inverter. NC if external
40
XTALN OP Clock used. Digital +3.3V supply rail. This pin should be decoupled to DVss by
41
DVdd PWR capacitors mounted close to the device pins.
42
COMMAND DATA IP C-BUS: Serial data input from the µC C-BUS: A 3-state C-BUS serial data output to the µC. This output is
43
REPLY DATA TS OP high impedance when not sending data to the µC.
44
FSO BI SPI bus Chip Select
45
DVss PWR Digital Ground
46
SERIAL CLOCK IP C-BUS: The C-BUS serial clock input from the µC
47
SYSCLK2 OP Synthesized Digital System Clock Output 2
48
CSN IP C-BUS: The C-BUS chip select input from the µC On this device, the exposed central metal pad may be electrically EXPOSED unconnected or, alternatively, may be connected to Analogue METAL PAD SUBSTRATE ~ Ground (AVss).
No other electrical connection is permitted. Notes:
IP = Input (+ PU/PD = internal pullup / pulldown resistor) OP = Output BI = Bidirectional TS OP = 3-state Output PWR = Power Connection NC = No Connection - should NOT be connected to any signal. 2019 CML Microsystems Plc Page 6 D/7146/1 Document Outline Datasheet Front Page 1 Brief Description 1.1 History 2 Signal List 3 External Components 4 PCB Layout Guidelines and Power Supply Decoupling 5 General Description 5.1 CMX7146 Features 6 Detailed Descriptions 6.1 Xtal Frequency 6.2 Host Interface 6.2.1 C-BUS Operation 6.3 Function Image Loading 6.3.1 FI Loading from Host Controller 6.3.2 FI Loading from Flash/EEPROM 6.4 Device Control 6.4.1 Device Configuration (using the Programming Register) 6.4.2 Device Configuration (using dedicated registers) 6.4.3 Interrupt Operation 6.4.4 Signal Routing 6.4.5 Loading Transmit Data 6.4.6 The Transmit Sequence 6.4.7 Other Modem Modes 6.4.8 Data Transfer 6.4.9 Raw Data Transfer 6.4.10 Pre-loading transmit data 6.4.11 Auxiliary clock rates 6.4.12 Auxiliary data 6.4.13 GPIO Pin Operation 6.4.14 Auxiliary ADC Operation 6.4.15 Auxiliary DAC / RAMDAC Operation 6.5 Digital System Clock Generators 6.5.1 System Clock Operation 6.6 Signal Level Optimisation 6.7 C-BUS Register Summary 7 CMX7146 FI-1.x Features 7.1 Modulation 7.2 Radio Interface 7.3 Transmit Performance 8 Performance Specification 8.1 Electrical Performance 8.1.1 Absolute Maximum Ratings 8.1.2 Operating Limits 8.1.3 Operating Characteristics 8.1.4 Parametric Performance 8.2 C-BUS Timing 8.3 Packaging END OF DOCUMENT
