Datasheet CMX7146 (CML Microcircuits) - 9
| Manufacturer | CML Microcircuits |
| Description | BPSK Wireless Data Modulator |
| Pages / Page | 37 / 9 — PCB Layout Guidelines and Power Supply Decoupling. Digital Ground Plane. … |
| File Format / Size | PDF / 2.1 Mb |
| Document Language | English |
PCB Layout Guidelines and Power Supply Decoupling. Digital Ground Plane. Analogue Ground Plane
Model Line for this Datasheet
Text Version of Document
link to page 7 BPSK Wireless Data Modulator CMX7146
4 PCB Layout Guidelines and Power Supply Decoupling
DVDD + C20 C21 C22 S SV
Digital Ground Plane
D DVSS DVSS DVSS C3 S D C S S D E S V V D V D D V D DVSS 1 2 AVSS AVSS 3 4 AVDD 5 AVDD 6 DVSS + 7 CMX7146Q3 C17 C18 C19 DV 8 SS VDEC AVSS AVSS AVSS 9 10 11 VBIAS 12 13 14 15 16 17 18 C7 S S S S AV V V SS D A AVSS +
Analogue Ground Plane
C24 C23 DVSS DVSS DVSS
Figure 3 CMX7146 Power Supply and De-coupling
Component Values as per Figure 2. Notes: It is important to protect the analogue pins from extraneous in-band noise and to minimise the impedance between the CMX7146 and the supply and bias de-coupling capacitors. The de-coupling capacitors C3, C7, C18, C19, C21, C22, C24 and C25 should be as close as possible to the CMX7146. It is therefore recommended that the printed circuit board is laid out with separate ground planes for the AVSS and DVSS supplies in the area of the CMX7146 with provision to make links between them, close to the CMX7146. Use of a multi-layer printed circuit board will facilitate the provision of ground planes on separate layers. VBIAS is used as an internal reference for detecting and generating the various analogue signals. It must be carefully decoupled, to ensure its integrity, so apart from the decoupling capacitor shown, no other loads should be connected. If VBIAS needs to be used to set the discriminator mid-point reference, it must be buffered with a high input impedance buffer. The crystal, X1, may be replaced with an external clock source. 2019 CML Microsystems Plc Page 9 D/7146/1 Document Outline Datasheet Front Page 1 Brief Description 1.1 History 2 Signal List 3 External Components 4 PCB Layout Guidelines and Power Supply Decoupling 5 General Description 5.1 CMX7146 Features 6 Detailed Descriptions 6.1 Xtal Frequency 6.2 Host Interface 6.2.1 C-BUS Operation 6.3 Function Image Loading 6.3.1 FI Loading from Host Controller 6.3.2 FI Loading from Flash/EEPROM 6.4 Device Control 6.4.1 Device Configuration (using the Programming Register) 6.4.2 Device Configuration (using dedicated registers) 6.4.3 Interrupt Operation 6.4.4 Signal Routing 6.4.5 Loading Transmit Data 6.4.6 The Transmit Sequence 6.4.7 Other Modem Modes 6.4.8 Data Transfer 6.4.9 Raw Data Transfer 6.4.10 Pre-loading transmit data 6.4.11 Auxiliary clock rates 6.4.12 Auxiliary data 6.4.13 GPIO Pin Operation 6.4.14 Auxiliary ADC Operation 6.4.15 Auxiliary DAC / RAMDAC Operation 6.5 Digital System Clock Generators 6.5.1 System Clock Operation 6.6 Signal Level Optimisation 6.7 C-BUS Register Summary 7 CMX7146 FI-1.x Features 7.1 Modulation 7.2 Radio Interface 7.3 Transmit Performance 8 Performance Specification 8.1 Electrical Performance 8.1.1 Absolute Maximum Ratings 8.1.2 Operating Limits 8.1.3 Operating Characteristics 8.1.4 Parametric Performance 8.2 C-BUS Timing 8.3 Packaging END OF DOCUMENT
4 PCB Layout Guidelines and Power Supply Decoupling
DVDD + C20 C21 C22 S SV
Digital Ground Plane
D DVSS DVSS DVSS C3 S D C S S D E S V V D V D D V D DVSS 1 2 AVSS AVSS 3 4 AVDD 5 AVDD 6 DVSS + 7 CMX7146Q3 C17 C18 C19 DV 8 SS VDEC AVSS AVSS AVSS 9 10 11 VBIAS 12 13 14 15 16 17 18 C7 S S S S AV V V SS D A AVSS +
Analogue Ground Plane
C24 C23 DVSS DVSS DVSS
Figure 3 CMX7146 Power Supply and De-coupling
Component Values as per Figure 2. Notes: It is important to protect the analogue pins from extraneous in-band noise and to minimise the impedance between the CMX7146 and the supply and bias de-coupling capacitors. The de-coupling capacitors C3, C7, C18, C19, C21, C22, C24 and C25 should be as close as possible to the CMX7146. It is therefore recommended that the printed circuit board is laid out with separate ground planes for the AVSS and DVSS supplies in the area of the CMX7146 with provision to make links between them, close to the CMX7146. Use of a multi-layer printed circuit board will facilitate the provision of ground planes on separate layers. VBIAS is used as an internal reference for detecting and generating the various analogue signals. It must be carefully decoupled, to ensure its integrity, so apart from the decoupling capacitor shown, no other loads should be connected. If VBIAS needs to be used to set the discriminator mid-point reference, it must be buffered with a high input impedance buffer. The crystal, X1, may be replaced with an external clock source. 2019 CML Microsystems Plc Page 9 D/7146/1 Document Outline Datasheet Front Page 1 Brief Description 1.1 History 2 Signal List 3 External Components 4 PCB Layout Guidelines and Power Supply Decoupling 5 General Description 5.1 CMX7146 Features 6 Detailed Descriptions 6.1 Xtal Frequency 6.2 Host Interface 6.2.1 C-BUS Operation 6.3 Function Image Loading 6.3.1 FI Loading from Host Controller 6.3.2 FI Loading from Flash/EEPROM 6.4 Device Control 6.4.1 Device Configuration (using the Programming Register) 6.4.2 Device Configuration (using dedicated registers) 6.4.3 Interrupt Operation 6.4.4 Signal Routing 6.4.5 Loading Transmit Data 6.4.6 The Transmit Sequence 6.4.7 Other Modem Modes 6.4.8 Data Transfer 6.4.9 Raw Data Transfer 6.4.10 Pre-loading transmit data 6.4.11 Auxiliary clock rates 6.4.12 Auxiliary data 6.4.13 GPIO Pin Operation 6.4.14 Auxiliary ADC Operation 6.4.15 Auxiliary DAC / RAMDAC Operation 6.5 Digital System Clock Generators 6.5.1 System Clock Operation 6.6 Signal Level Optimisation 6.7 C-BUS Register Summary 7 CMX7146 FI-1.x Features 7.1 Modulation 7.2 Radio Interface 7.3 Transmit Performance 8 Performance Specification 8.1 Electrical Performance 8.1.1 Absolute Maximum Ratings 8.1.2 Operating Limits 8.1.3 Operating Characteristics 8.1.4 Parametric Performance 8.2 C-BUS Timing 8.3 Packaging END OF DOCUMENT
