Datasheet ADA4558 (Analog Devices) - 5

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Data Sheet ADA4558 Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE Start-Up Time (System) First readback of valid data, filter 100 ms setting = 500 Hz, all faults enabled or disabled Main Oscillator Frequency All internal timers are related to 9.5 10 10.5 MHz oscillator Oscillator Frequency (Sleep Mode) 300 kHz ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM) Programming Number of Cycles 1000 Cycles Time Per 32-bit written word 20 40 ms Temperature −40 +150 °C Data Retention 1000 write cycles, operation at 150°C 10 Years 1000 write cycles, 40,000 hour 15 Years operation (10,000 hours at 55°C + 27,000 hours at 125°C + 3000 hours at 150°C) FAULTS Bridge Sensor Input Bias Current IB Detects input open circuit (startup) 5 µA Detects input open circuit, 300 nA normal/running mode operation (EEPROM register PGA_ADD_PULUP_150 = 0), default Detects input open circuit, 450 nA normal/running mode operation (EEPROM register PGA_ADD_PULUP_150 = 1) Input Open Detection Resistance Startup 320 kΩ Normal running mode operation 32 MΩ Open Detection Threshold Low 18.75 % VREG High 81.25 % VREG Input Short Detection Resistance 0.5 kΩ Oscillator Crosscheck Limit 14 % External Temperature Sensor Bias Detects external temperature open 28 nA Current circuit Thermal Shutdown TSD 170 °C Hysteresis TSD_HY 7 °C 1 Guaranteed by absolute maximum ratings (see the Absolute Maximum Ratings section). 2 The VREG voltage is also the reference to the ADC. Therefore, reference temperature drift does not affect system error. This specification can be useful in gain and offset selection at EOL calibration. 3 Guaranteed by design. 4 Errors in PGA, temperature sensor gain, offset, and temperature drift are eliminated based on the EOL calibration routine. 5 The input offset trim range is −60 mV/V to +60 mV/V. The ADC reference is 4 V. The resulting input offset trim range is 0.48 V. The output preferred offset trim resolution is 31 mV. For a gain of 2.9, the input referred offset trim resolution is 10.6 mV. Dividing range by resolution gives approximately 50 steps, which is close to a 6-bit resolution. For a gain of 971, the input referred offset trim resolution is 32 μV. Dividing range by resolution equals 16,287 LSBs, which is close to 14-bit resolution. In all cases, this only provides the coarse offset calibration required to get the PGA output into the valid ADC range of operation. The digital linearization engine provides fine offset calibration to meet the system accuracy targets. Rev. 0 | Page 5 of 12 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION TYPICAL CONNECTION DIAGRAM EMC PERFORMANCE PCB LAYOUT GUIDELINES OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS