Datasheet AD7741 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Single and Multichannel, Synchronous Voltage-to-Frequency Converters |
| Pages / Page | 13 / 6 — AD7741. AD7742 PIN FUNCTION DESCRIPTION. Pin No. Mnemonic. Function. PIN … |
| Revision | A |
| File Format / Size | PDF / 238 Kb |
| Document Language | English |
AD7741. AD7742 PIN FUNCTION DESCRIPTION. Pin No. Mnemonic. Function. PIN CONFIGURATION. OUT. GAIN. GND 3. 14 VIN4. A1 4. AD7742. 13 VIN3
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AD7741 AD7742 PIN FUNCTION DESCRIPTION Pin No. Mnemonic Function
1 fOUT Frequency Output. This pin provides the output of the synchronous VFC. 2 VDD Power Supply Input. These parts can be operated from +4.75 V to +5.25 V and the supply should be adequately decoupled to GND. 3 GND Ground reference point for all circuitry on the part. 4–5 A1, A0 Address Inputs used to select the input channel configuration. 6 CLKOUT External Clock Output. When the master clock for the device is a crystal, the crystal is connected be- tween CLKIN and CLKOUT. When an external clock is applied to CLKIN, the CLKOUT pin provides an inverted clock signal. This clock should be buffered if it is to be used as a clock source elsewhere in the system. 7 CLKIN External Clock Input. The master clock for the device can be provided in the form of a crystal or an external clock. A crystal may be tied across the CLKIN and CLKOUT pins. Alternatively, the CLKIN pin may be driven by a CMOS-compatible clock and CLKOUT left unconnected. The frequency of the master clock may be as high as 6 MHz. 8 UNI/BIP Control input which determines whether the device operates with differential bipolar analog input signals or differential unipolar analog input signals. 9 REFOUT 2.5 V Voltage Reference Output. This can be tied directly to REFIN. It may also be used as a reference to other parts of the system provided it is buffered first. 10 REFIN This is the Reference Input to the core of the VFC and defines the span of the VFC. A 2.5 V reference is required at this pin. This may be provided by connecting it directly to REFOUT or by using a preci- sion external reference (e.g., REF192). 11 VIN1 Buffered Analog Input Channel 1. This is either a pseudo-differential input with respect to VIN4 or it is the positive input of a truly-differential input pair with respect to VIN2. 12 VIN2 Buffered Analog Input Channel 2. This is either a pseudo-differential input with respect to VIN4 or it is the negative input of a truly-differential input pair with respect to VIN1. 13 VIN3 Buffered Analog Input Channel 3. This is the positive input of a truly-differential input pair with re- spect to VIN4. 14 VIN4 Buffered Analog Input Channel 4. This is either the common for pseudo-differential input with respect to VIN1 or VIN2 or it is the negative input of a truly-differential input pair with respect to VIN3. 15 GAIN Gain Select input that controls whether the gain on the analog front-end is X1 or X2. 16 PD Active Low Power-Down pin. When this input is low, the part enters power-down mode where it typi- cally consumes 25 μA of current.
PIN CONFIGURATION f 1 16 OUT PD V 2 15 DD GAIN GND 3 14 VIN4 A1 4 AD7742 13 VIN3 TOP VIEW A0 5 (Not to Scale) 12 VIN2 CLKOUT 6 11 VIN1 CLKIN 7 10 REFIN UNI/ 8 9 BIP REFOUT
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1 fOUT Frequency Output. This pin provides the output of the synchronous VFC. 2 VDD Power Supply Input. These parts can be operated from +4.75 V to +5.25 V and the supply should be adequately decoupled to GND. 3 GND Ground reference point for all circuitry on the part. 4–5 A1, A0 Address Inputs used to select the input channel configuration. 6 CLKOUT External Clock Output. When the master clock for the device is a crystal, the crystal is connected be- tween CLKIN and CLKOUT. When an external clock is applied to CLKIN, the CLKOUT pin provides an inverted clock signal. This clock should be buffered if it is to be used as a clock source elsewhere in the system. 7 CLKIN External Clock Input. The master clock for the device can be provided in the form of a crystal or an external clock. A crystal may be tied across the CLKIN and CLKOUT pins. Alternatively, the CLKIN pin may be driven by a CMOS-compatible clock and CLKOUT left unconnected. The frequency of the master clock may be as high as 6 MHz. 8 UNI/BIP Control input which determines whether the device operates with differential bipolar analog input signals or differential unipolar analog input signals. 9 REFOUT 2.5 V Voltage Reference Output. This can be tied directly to REFIN. It may also be used as a reference to other parts of the system provided it is buffered first. 10 REFIN This is the Reference Input to the core of the VFC and defines the span of the VFC. A 2.5 V reference is required at this pin. This may be provided by connecting it directly to REFOUT or by using a preci- sion external reference (e.g., REF192). 11 VIN1 Buffered Analog Input Channel 1. This is either a pseudo-differential input with respect to VIN4 or it is the positive input of a truly-differential input pair with respect to VIN2. 12 VIN2 Buffered Analog Input Channel 2. This is either a pseudo-differential input with respect to VIN4 or it is the negative input of a truly-differential input pair with respect to VIN1. 13 VIN3 Buffered Analog Input Channel 3. This is the positive input of a truly-differential input pair with re- spect to VIN4. 14 VIN4 Buffered Analog Input Channel 4. This is either the common for pseudo-differential input with respect to VIN1 or VIN2 or it is the negative input of a truly-differential input pair with respect to VIN3. 15 GAIN Gain Select input that controls whether the gain on the analog front-end is X1 or X2. 16 PD Active Low Power-Down pin. When this input is low, the part enters power-down mode where it typi- cally consumes 25 μA of current.
PIN CONFIGURATION f 1 16 OUT PD V 2 15 DD GAIN GND 3 14 VIN4 A1 4 AD7742 13 VIN3 TOP VIEW A0 5 (Not to Scale) 12 VIN2 CLKOUT 6 11 VIN1 CLKIN 7 10 REFIN UNI/ 8 9 BIP REFOUT
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