Datasheet TB67S112PG (Toshiba) - 10
| Manufacturer | Toshiba |
| Description | BiCD Process Integrated Circuit Silicon Monolithic |
| Pages / Page | 15 / 10 — AC Electrical Characteristics (Ta = 25°C, VM = 24 V, unless otherwise … |
| File Format / Size | PDF / 352 Kb |
| Document Language | English |
AC Electrical Characteristics (Ta = 25°C, VM = 24 V, unless otherwise specified). Timing chart of AC characteristics
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TB67S112PG
AC Electrical Characteristics (Ta = 25°C, VM = 24 V, unless otherwise specified)
Characteristics Symbol Test condition Min Typ. Max Unit tIN(twp) (Design value) 500 ― ― ns Minimum pulse width of logic input tIN(twn) (Design value) 500 ― ― ns Output MOSFET switching tr L=350mH,R=84Ω 50 100 200 ns characteristics tf L=350mH,R=84Ω 40 80 160 ns tpLH(IN) Between IN and OUT , Output MOSFET response OUT: pull-up(2kΩ/VM) ― 500 ― ns characteristics tpHL(IN) Between IN and OUT, OUT: pull-up(2kΩ/VM) ― 500 ― ns Over current detection (ISD) masking time tISD(mask) ― ― 1.25 ― μs Off time after over current detection (ISD) ― ― ― 3 ― ms Thermal shutdown (TSD) masking time tTSD(mask) ― 2.0 5.0 8.0 μs
Timing chart of AC characteristics
tIN(twn) IN1 50% 50% 50% IN2 tIN(twp) tpLH(IN) tpHL(IN) 90% 90% OUT1 OUT2 50% 50% 10% 10% tf tr Timing charts may be simplified for explanatory purposes. 10 2019-07-08
AC Electrical Characteristics (Ta = 25°C, VM = 24 V, unless otherwise specified)
Characteristics Symbol Test condition Min Typ. Max Unit tIN(twp) (Design value) 500 ― ― ns Minimum pulse width of logic input tIN(twn) (Design value) 500 ― ― ns Output MOSFET switching tr L=350mH,R=84Ω 50 100 200 ns characteristics tf L=350mH,R=84Ω 40 80 160 ns tpLH(IN) Between IN and OUT , Output MOSFET response OUT: pull-up(2kΩ/VM) ― 500 ― ns characteristics tpHL(IN) Between IN and OUT, OUT: pull-up(2kΩ/VM) ― 500 ― ns Over current detection (ISD) masking time tISD(mask) ― ― 1.25 ― μs Off time after over current detection (ISD) ― ― ― 3 ― ms Thermal shutdown (TSD) masking time tTSD(mask) ― 2.0 5.0 8.0 μs
Timing chart of AC characteristics
tIN(twn) IN1 50% 50% 50% IN2 tIN(twp) tpLH(IN) tpHL(IN) 90% 90% OUT1 OUT2 50% 50% 10% 10% tf tr Timing charts may be simplified for explanatory purposes. 10 2019-07-08
