Datasheet SPD50P03L G (Infineon) - 2
| Manufacturer | Infineon |
| Description | OptiMOS -P Power-Transistor |
| Pages / Page | 9 / 2 — SPD50P03L G. Parameter. Symbol Conditions. Values. Unit. min. typ. max. … |
| Revision | 01_09 |
| File Format / Size | PDF / 395 Kb |
| Document Language | English |
SPD50P03L G. Parameter. Symbol Conditions. Values. Unit. min. typ. max. Thermal characteristics. Electrical characteristics,
Model Line for this Datasheet
Text Version of Document
SPD50P03L G Parameter Symbol Conditions Values Unit min. typ. max. Thermal characteristics
Thermal resistance, junction - case R thJC - - 1 K/W R thJA minimal footprint - - 75 Thermal resistance, junction - ambient 6 cm2 cooling area2) - - 50
Electrical characteristics,
at T j=25 °C, unless otherwise specified
Static characteristics
Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D=-250 µA -30 - - V V Gate threshold voltage V DS=V GS, GS(th) -1 -1.5 -2 I D=-250 µA V Zero gate voltage drain current I DS=-30 V, V GS=0 V, DSS - -0.1 -1 µA T j=25 °C V DS=-30 V, V GS=0 V, - -10 -100 T j=175 °C Gate-source leakage current I GSS V GS=-20 V, V DS=0 V - -10 -100 nA V Drain-source on-state resistance R GS=-4.5 V, DS(on) - 8.5 12.5 mΩ I D=-30 A Drain-source on-state resistance R DS(on) V GS=-10 V, I D=-50 A - 5.7 7.0 |V Transconductance g DS|>2|I D|R DS(on)max, fs 47 94 - S I D=-50 A 1) Current is limited by bondwire; with an R thJC=1 K/W the chip is able to carry 123 A. 2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.9 page 2 2012-09-13 Document Outline Untitled
Thermal resistance, junction - case R thJC - - 1 K/W R thJA minimal footprint - - 75 Thermal resistance, junction - ambient 6 cm2 cooling area2) - - 50
Electrical characteristics,
at T j=25 °C, unless otherwise specified
Static characteristics
Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D=-250 µA -30 - - V V Gate threshold voltage V DS=V GS, GS(th) -1 -1.5 -2 I D=-250 µA V Zero gate voltage drain current I DS=-30 V, V GS=0 V, DSS - -0.1 -1 µA T j=25 °C V DS=-30 V, V GS=0 V, - -10 -100 T j=175 °C Gate-source leakage current I GSS V GS=-20 V, V DS=0 V - -10 -100 nA V Drain-source on-state resistance R GS=-4.5 V, DS(on) - 8.5 12.5 mΩ I D=-30 A Drain-source on-state resistance R DS(on) V GS=-10 V, I D=-50 A - 5.7 7.0 |V Transconductance g DS|>2|I D|R DS(on)max, fs 47 94 - S I D=-50 A 1) Current is limited by bondwire; with an R thJC=1 K/W the chip is able to carry 123 A. 2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.9 page 2 2012-09-13 Document Outline Untitled
