Datasheet AD7711A (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | LC2MOS Signal Conditioning ADC with RTD Current Source |
| Pages / Page | 28 / 6 — AD7711A TIMING CHARACTERISTICS (continued). Limit at TMIN, TMAX. … |
| File Format / Size | PDF / 396 Kb |
| Document Language | English |
AD7711A TIMING CHARACTERISTICS (continued). Limit at TMIN, TMAX. Parameter. (A, S Versions). Unit. Conditions/Comments
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Text Version of Document
AD7711A TIMING CHARACTERISTICS (continued) Limit at TMIN, TMAX Parameter (A, S Versions) Unit Conditions/Comments
External Clocking Mode fSCLK fCLK IN/5 MHz max Serial Clock Input Frequency t20 0 ns min DRDY to RFS Setup Time t21 0 ns min DRDY to RFS Hold Time t22 2 ¥ tCLK IN ns min A0 to RFS Setup Time t23 0 ns min A0 to RFS Hold Time t 7 24 4 ¥ tCLK IN ns max Data Access Time (RFS Low to Data Valid) t 7 25 10 ns min SCLK Falling Edge to Data Valid Delay 2 ¥ tCLK IN + 20 ns max t26 2 ¥ tCLK IN ns min SCLK High Pulse Width t27 2 ¥ tCLK IN ns min SCLK Low Pulse Width t28 tCLK IN + 10 ns max SCLK Falling Edge to DRDY High t 8 29 10 ns min SCLK to Data Valid Hold Time tCLK IN + 10 ns max t30 10 ns min RFS/TFS to SCLK Falling Edge Hold Time t 8 31 5 ¥ tCLK IN/2 + 50 ns max RFS to Data Valid Hold Time t32 0 ns min A0 to TFS Setup Time t33 0 ns min A0 to TFS Hold Time t34 4 ¥ tCLK IN ns min SCLK Falling Edge to TFS Hold Time t35 2 ¥ tCLK IN – SCLK High ns min Data Valid to SCLK Setup Time t36 30 ns min Data Valid to SCLK Hold Time NOTES 7These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V. 8These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Specifications subject to change without notice.
PIN CONFIGURATION 1.6mA DIP and SOIC TO OUTPUT 2.1V PIN 100pF SCLK 1 24 DGND MCLK IN 2 23 DVDD 200
m
A MCLK OUT 3 22 SDATA A0 4 21 DRDY
Figure 1. Load Circuit for Access Time and Bus
SYNC 5 20 RFS
Relinquish Time
AD7711A MODE 6 TFS TOP VIEW 19 (Not to Scale) AIN1(+) 7 18 AGND AIN1(–) 8 17 RTD CURRENT AIN2(+) 9 16 REF OUT AIN2(–) 10 15 REF IN(+) V 11 14 SS REF IN(–) AV 12 13 DD VBIAS
–6– REV. D
External Clocking Mode fSCLK fCLK IN/5 MHz max Serial Clock Input Frequency t20 0 ns min DRDY to RFS Setup Time t21 0 ns min DRDY to RFS Hold Time t22 2 ¥ tCLK IN ns min A0 to RFS Setup Time t23 0 ns min A0 to RFS Hold Time t 7 24 4 ¥ tCLK IN ns max Data Access Time (RFS Low to Data Valid) t 7 25 10 ns min SCLK Falling Edge to Data Valid Delay 2 ¥ tCLK IN + 20 ns max t26 2 ¥ tCLK IN ns min SCLK High Pulse Width t27 2 ¥ tCLK IN ns min SCLK Low Pulse Width t28 tCLK IN + 10 ns max SCLK Falling Edge to DRDY High t 8 29 10 ns min SCLK to Data Valid Hold Time tCLK IN + 10 ns max t30 10 ns min RFS/TFS to SCLK Falling Edge Hold Time t 8 31 5 ¥ tCLK IN/2 + 50 ns max RFS to Data Valid Hold Time t32 0 ns min A0 to TFS Setup Time t33 0 ns min A0 to TFS Hold Time t34 4 ¥ tCLK IN ns min SCLK Falling Edge to TFS Hold Time t35 2 ¥ tCLK IN – SCLK High ns min Data Valid to SCLK Setup Time t36 30 ns min Data Valid to SCLK Hold Time NOTES 7These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V. 8These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Specifications subject to change without notice.
PIN CONFIGURATION 1.6mA DIP and SOIC TO OUTPUT 2.1V PIN 100pF SCLK 1 24 DGND MCLK IN 2 23 DVDD 200
m
A MCLK OUT 3 22 SDATA A0 4 21 DRDY
Figure 1. Load Circuit for Access Time and Bus
SYNC 5 20 RFS
Relinquish Time
AD7711A MODE 6 TFS TOP VIEW 19 (Not to Scale) AIN1(+) 7 18 AGND AIN1(–) 8 17 RTD CURRENT AIN2(+) 9 16 REF OUT AIN2(–) 10 15 REF IN(+) V 11 14 SS REF IN(–) AV 12 13 DD VBIAS
–6– REV. D
