PIC16(L)F170X/171X (Microchip) - 10
| Manufacturer | Microchip |
| Description | Cost Effective 8-Bit Intelligent Analog Flash Microcontrollers |
| Pages / Page | 18 / 10 — PIC16(L)F170X/171X. TABLE 3:. 20-PIN ALLOCATION TABLE (PIC16(L)F1707). … |
| File Format / Size | PDF / 449 Kb |
| Document Language | English |
PIC16(L)F170X/171X. TABLE 3:. 20-PIN ALLOCATION TABLE (PIC16(L)F1707). OIC/. ros. SSP. rru. ll-. sic. I/O. SSO. ADC. fere. ime. CCP. ro C. (1). (3). d va
Model Line for this Datasheet
- PIC16F1703-E/ML PIC16F1703-E/P PIC16F1703-E/PVAO PIC16F1703-E/SL PIC16F1703-E/ST PIC16F1703-E/STVAO PIC16F1703-I/ML PIC16F1703-I/P PIC16F1703-I/SL PIC16F1703-I/ST PIC16F1703T-E/STVAO PIC16F1703T-I/ML PIC16F1703T-I/SL PIC16F1703T-I/ST
- PIC16F1704-E/ML PIC16F1704-E/MLVAO PIC16F1704-E/P PIC16F1704-E/SL PIC16F1704-E/SLVAO PIC16F1704-E/ST PIC16F1704-E/STVAO PIC16F1704-I/JQ PIC16F1704-I/ML PIC16F1704-I/MLVAO PIC16F1704-I/P PIC16F1704-I/SL PIC16F1704-I/SLVAO PIC16F1704-I/ST PIC16F1704T-E/ML PIC16F1704T-E/MLVAO PIC16F1704T-E/SL PIC16F1704T-E/SLVAO PIC16F1704T-E/STVAO PIC16F1704T-I/ML PIC16F1704T-I/MLVAO PIC16F1704T-I/SL PIC16F1704T-I/SLVAO PIC16F1704T-I/ST PIC16F1704T-I/STVAO
- PIC16F1705-E/ML PIC16F1705-E/P PIC16F1705-E/SL PIC16F1705-E/ST PIC16F1705-E/STVAO PIC16F1705-I/ML PIC16F1705-I/MLVAO PIC16F1705-I/P PIC16F1705-I/SL PIC16F1705-I/ST PIC16F1705-I/STVAO PIC16F1705T-E/SL PIC16F1705T-E/ST PIC16F1705T-E/STVAO PIC16F1705T-I/ML PIC16F1705T-I/MLVAO PIC16F1705T-I/SL PIC16F1705T-I/ST PIC16F1705T-I/STVAO
- PIC16F1707-E/ML PIC16F1707-E/P PIC16F1707-E/SO PIC16F1707-E/SS PIC16F1707-I/ML PIC16F1707-I/P PIC16F1707-I/SO PIC16F1707-I/SS PIC16F1707T-I/SO
- PIC16F1708-E/ML PIC16F1708-E/P PIC16F1708-E/SO PIC16F1708-E/SS PIC16F1708-E/SSVAO PIC16F1708-I/GZ PIC16F1708-I/ML PIC16F1708-I/P PIC16F1708-I/SO PIC16F1708-I/SS PIC16F1708T-E/ML PIC16F1708T-E/SS PIC16F1708T-E/SSVAO PIC16F1708T-I/ML PIC16F1708T-I/SO PIC16F1708T-I/SS
- PIC16F1709-E/ML PIC16F1709-E/P PIC16F1709-E/SO PIC16F1709-E/SS PIC16F1709-I/ML PIC16F1709-I/P PIC16F1709-I/SO PIC16F1709-I/SS PIC16F1709T-E/SS PIC16F1709T-I/ML PIC16F1709T-I/SO PIC16F1709T-I/SS
- PIC16F1713-E/ML PIC16F1713-E/MV PIC16F1713-E/SO PIC16F1713-E/SP PIC16F1713-E/SS PIC16F1713-I/ML PIC16F1713-I/MV PIC16F1713-I/SO PIC16F1713-I/SP PIC16F1713-I/SS PIC16F1713-I/SSVAO PIC16F1713T-E/MV PIC16F1713T-E/MVVAO PIC16F1713T-I/ML PIC16F1713T-I/MV PIC16F1713T-I/SO PIC16F1713T-I/SS PIC16F1713T-I/SSVAO
- PIC16F1716-E/ML PIC16F1716-E/MV PIC16F1716-E/SO PIC16F1716-E/SP PIC16F1716-E/SS PIC16F1716-I/ML PIC16F1716-I/MV PIC16F1716-I/SO PIC16F1716-I/SP PIC16F1716-I/SS PIC16F1716T-E/MVVAO PIC16F1716T-I/ML PIC16F1716T-I/MV PIC16F1716T-I/SO PIC16F1716T-I/SS
- PIC16F1717-E/ML PIC16F1717-E/MV PIC16F1717-E/P PIC16F1717-E/PT PIC16F1717-I/ML PIC16F1717-I/MV PIC16F1717-I/P PIC16F1717-I/PT PIC16F1717T-E/MVVAO PIC16F1717T-I/ML PIC16F1717T-I/MV PIC16F1717T-I/PT
Text Version of Document
DS4
PIC16(L)F170X/171X TABLE 3: 20-PIN ALLOCATION TABLE (PIC16(L)F1707)
0001708A-p
s ce p t ) OIC/ P n rs p p (2 N ros u /S Am SSP rru ll- sic I/O IP SSO QF ADC fere ime CCP M te u Ba D Op ro C T In P P Re Ze
age 10 RA0 19 16 AN0 VREF- — — — — — IOC Y ICSPDAT RA1 18 15 AN1 VREF+ — — — — — IOC Y ICSPCLK RA2 17 14 AN2 — — ZCD T0CKI
(1)
— — INT
(1)
Y — IOC RA3 4 1 — — — — — — — IOC Y MCLR VPP RA4 3 20 AN3 — — — T1G
(1)
— — IOC Y CLKOUT RA5 2 19 — — — — T1CKI — — IOC Y CLKIN RB4 13 10 AN10 — OPA1IN- — — — SCK
(1)
IOC Y — SDA
(3) A
RB5 12 9 AN11 — OPA1IN+ — — — — IOC Y —
d va
RB6 11 8 — — — — — — SDI
(1)
IOC Y — SCL
(3) nce Inf
RB7 10 7 — — — — — — — IOC Y — RC0 16 13 AN4 — — — — — — IOC Y — RC1 15 12 AN5 — — — — — — IOC Y —
o r
RC2 14 11 AN6 — OPA1OUT — — — — IOC Y —
m
RC3 7 4 AN7 — OPA2OUT — — CCP2
(1)
— IOC Y —
at ion
RC4 6 3 — — OPA2IN- — — — — IOC Y — RC5 5 2 — — OPA2IN+ — — CCP1
(1)
— IOC Y — RC6 8 5 AN8 — — — — — SS
(1)
IOC Y — RC7 9 6 AN9 — — — — — — IOC Y — VDD 1 18 — — — — — — — — — VDD VSS 20 17 — — — — — — — — — VSS — — — — — — — CPP1 SDA
(3)
— — — 20 — — — — — — — CPP2 SCL
(3)
— — — 13 M OUT
(2)
SCK — — — — — — — — SDO — — — icrochip
Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
All pin digital outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registers.
3:
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. T e chnology Inc. Document Outline Description: Core Features: Memory: Operating Characteristics: eXtreme Low-Power (XLP) Features: - 8 uA @ 32 kHz, 1.8V, typical - 32 uA/MHz @ 1.8V, typical Digital Peripherals: Intelligent Analog Peripherals: Clocking Structure: Programming/Debug Features: TABLE 1: 14-Pin and 16-Pin Allocation Table (PIC16(L)F1703) TABLE 2: 14-Pin and 16-Pin Allocation Table (PIC16(L)F1704/5) TABLE 3: 20-Pin Allocation Table (PIC16(L)F1707) TABLE 4: 20-Pin Allocation Table (PIC16(L)F1708/9) TABLE 5: 28-Pin Allocation Table (PIC16L(F)1713/6/8) (Part 1) TABLE 6: 28-Pin Allocation Table (PIC16L(F)1713/6/8) (Part 2) TABLE 7: Pin Allocation Table (PIC16L(F)1717/9) (Part 1) TABLE 8: Pin Allocation Table (PIC16L(F)1717/9) (Part 2 Trademarks Worldwide Sales
PIC16(L)F170X/171X TABLE 3: 20-PIN ALLOCATION TABLE (PIC16(L)F1707)
0001708A-p
s ce p t ) OIC/ P n rs p p (2 N ros u /S Am SSP rru ll- sic I/O IP SSO QF ADC fere ime CCP M te u Ba D Op ro C T In P P Re Ze
age 10 RA0 19 16 AN0 VREF- — — — — — IOC Y ICSPDAT RA1 18 15 AN1 VREF+ — — — — — IOC Y ICSPCLK RA2 17 14 AN2 — — ZCD T0CKI
(1)
— — INT
(1)
Y — IOC RA3 4 1 — — — — — — — IOC Y MCLR VPP RA4 3 20 AN3 — — — T1G
(1)
— — IOC Y CLKOUT RA5 2 19 — — — — T1CKI — — IOC Y CLKIN RB4 13 10 AN10 — OPA1IN- — — — SCK
(1)
IOC Y — SDA
(3) A
RB5 12 9 AN11 — OPA1IN+ — — — — IOC Y —
d va
RB6 11 8 — — — — — — SDI
(1)
IOC Y — SCL
(3) nce Inf
RB7 10 7 — — — — — — — IOC Y — RC0 16 13 AN4 — — — — — — IOC Y — RC1 15 12 AN5 — — — — — — IOC Y —
o r
RC2 14 11 AN6 — OPA1OUT — — — — IOC Y —
m
RC3 7 4 AN7 — OPA2OUT — — CCP2
(1)
— IOC Y —
at ion
RC4 6 3 — — OPA2IN- — — — — IOC Y — RC5 5 2 — — OPA2IN+ — — CCP1
(1)
— IOC Y — RC6 8 5 AN8 — — — — — SS
(1)
IOC Y — RC7 9 6 AN9 — — — — — — IOC Y — VDD 1 18 — — — — — — — — — VDD VSS 20 17 — — — — — — — — — VSS — — — — — — — CPP1 SDA
(3)
— — — 20 — — — — — — — CPP2 SCL
(3)
— — — 13 M OUT
(2)
SCK — — — — — — — — SDO — — — icrochip
Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
All pin digital outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registers.
3:
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. T e chnology Inc. Document Outline Description: Core Features: Memory: Operating Characteristics: eXtreme Low-Power (XLP) Features: - 8 uA @ 32 kHz, 1.8V, typical - 32 uA/MHz @ 1.8V, typical Digital Peripherals: Intelligent Analog Peripherals: Clocking Structure: Programming/Debug Features: TABLE 1: 14-Pin and 16-Pin Allocation Table (PIC16(L)F1703) TABLE 2: 14-Pin and 16-Pin Allocation Table (PIC16(L)F1704/5) TABLE 3: 20-Pin Allocation Table (PIC16(L)F1707) TABLE 4: 20-Pin Allocation Table (PIC16(L)F1708/9) TABLE 5: 28-Pin Allocation Table (PIC16L(F)1713/6/8) (Part 1) TABLE 6: 28-Pin Allocation Table (PIC16L(F)1713/6/8) (Part 2) TABLE 7: Pin Allocation Table (PIC16L(F)1717/9) (Part 1) TABLE 8: Pin Allocation Table (PIC16L(F)1717/9) (Part 2 Trademarks Worldwide Sales
