Datasheet PIC16F1717, PIC16F1718, PIC16F1719, PIC16LF1717, PIC16LF1718, PIC16LF1719 (Microchip) - 8

DS400017
PIC16(L)F1717/8/9 TABLE 2: 40/44-PIN ALLOCATION TABLE (PIC16(L)F1717/9) r s ce to p T s ) ra R c
40C-pag
(2 FP FN en M G DIP pa Am rrupt SSP SA asi I/O P imer CCP CLC e ullup TQ UQ ADC p DAC NCO PW CO efer ro Cros M B O T P R EU Int Com Ze
e 8 C1IN0- RA0 2 19 17 AN0 CLCIN0(1) IOC Y C2IN0- C1IN1- RA1 3 20 18 AN1 OPA1OUT CLCIN1(1) IOC Y C2IN1- C1IN0+ RA2 4 21 19 AN2 V5()- DAC1OUT1 IOC Y C2IN0+ RA3 5 22 20 AN3 V5()+ C1IN1+ IOC Y RA4 6 23 21 OPA1IN+ T0CKI(1) IOC Y RA5 7 24 22 AN4 OPA1IN- DAC2OUT1 nSS(1) IOC Y OSC2 RA6 14 31 29 IOC Y CLKOUT OSC1 RA7 13 30 28 IOC Y CLKIN INT(1) RB0 33 8 8 AN12 C2IN1+ ZCD COG1IN(1) Y IOC C1IN3- RB1 34 9 9 AN10 OPA2OUT IOC Y C2IN3- RB2 35 10 10 AN8 OPA2IN- IOC Y C1IN2- RB3 36 11 11 AN9 OPA2IN+ IOC Y C2IN2- RB4 37 14 12 AN11 IOC Y RB5 38 15 13 AN13 T1G(1) IOC Y RB6 39 16 14 CLCIN2(1) IOC Y ICSPCLK DAC1OUT2  RB7 40 17 15 CLCIN3(1) IOC Y ICSPDAT DAC2OUT2 2014- T1CKI(1) RC0 15 32 30 IOC Y SOSCO 2018 Microchip T RC1 16 35 31 SOSCI CCP2(1) IOC Y RC2 17 36 32 AN14 CCP1(1) IOC Y RC3 18 37 33 AN15 6&/SCK(1) IOC Y Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. e 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. chnolo 4: Alternate outputs are excluded from solid shaded areas. 5: Alternate inputs are excluded from dot shaded areas. gy Inc. Document Outline Description: Core Features: Memory: Operating Characteristics: eXtreme Low-Power (XLP) Features: Digital Peripherals: Intelligent Analog Peripherals: Clocking Structure: Programming/Debug Features: Pin Diagrams Table of Contents Most Current Data Sheet Errata Customer Notification System 1.0 Device Overview TABLE 1-1: Device Peripheral Summary 1.1 Register and Bit Naming Conventions 1.1.1 Register Names 1.1.2 Bit Names 1.1.3 Register and Bit Naming Exceptions FIGURE 1-1: PIC16(L)F1718 Block Diagram FIGURE 1-2: PIC16(L)F1717/9 Block Diagram TABLE 1-2: PIC16(L)F1718 Pinout Description TABLE 1-3: PIC16(L)F1717/9 Pinout Description 2.0 Enhanced Mid-Range CPU FIGURE 2-1: Core Block Diagram 2.1 Automatic Interrupt Context Saving 2.2 16-Level Stack with Overflow and Underflow 2.3 File Select Registers 2.4 Instruction Set 3.0 Memory Organization 3.1 Program Memory Organization 3.2 High-Endurance Flash TABLE 3-1: Device Sizes and Addresses FIGURE 3-1: Program Memory Map and Stack for PIC16(L)F1717 FIGURE 3-2: Program Memory Map and Stack for PIC16(L)F1718/9 3.2.1 Reading Program Memory as Data EXAMPLE 3-1: RETLW Instruction EXAMPLE 3-2: Accessing Program Memory Via FSR 3.3 Data Memory Organization 3.3.1 Core Registers TABLE 3-2: Core Registers 3.4 Register Definitions: Status Register 3-1: STATUS: STATUS Register 3.4.1 Special Function Register 3.4.2 General Purpose RAM 3.4.3 Common RAM FIGURE 3-3: Banked Memory Partitioning 3.4.4 Device Memory Maps TABLE 3-3: PIC16(L)F1718 Memory Map (Banks 0-7) TABLE 3-4: PIC16(L)F1717/9 Memory Map (Banks 0-7) TABLE 3-5: PIC16(L)F1717 Memory Map, Bank 8-23 TABLE 3-6: PIC16(L)F1718/9 Memory Map, Bank 8-23 TABLE 3-7: PIC16(L)F1717 Memory Map, Bank 24-31 TABLE 3-8: PIC16(L)F1718/9 Memory Map, Bank 24-31 TABLE 3-9: PIC16(L)F1717/8/9 Memory Map, Bank 28-30 TABLE 3-10: PIC16(L)F1717/8/9 Memory Map, Bank 31 3.4.5 Core Function Registers Summary TABLE 3-11: Core Function Registers Summary (1) TABLE 3-12: Special Function Register Summary 3.5 PCL and PCLATH FIGURE 3-4: Loading of PC in Different Situations 3.5.1 Modifying PCL 3.5.2 Computed GOTO 3.5.3 Computed Function Calls 3.5.4 Branching 3.6 Stack 3.6.1 Accessing the Stack FIGURE 3-5: Accessing the Stack Example 1 FIGURE 3-6: Accessing the Stack Example 2 FIGURE 3-7: Accessing the Stack Example 3 FIGURE 3-8: Accessing the Stack Example 4 3.6.2 Overflow/Underflow Reset 3.7 Indirect Addressing FIGURE 3-9: Indirect Addressing 3.7.1 Traditional Data Memory FIGURE 3-10: Traditional Data Memory Map 3.7.2 Linear Data Memory FIGURE 3-11: Linear Data Memory Map 3.7.3 Program Flash Memory FIGURE 3-12: Program Flash Memory Map 4.0 Device Configuration 4.1 Configuration Words 4.2 Register Definitions: Configuration Words Register 4-1: CONFIG1: Configuration Word 1 Register 4-2: CONFIG2: Configuration Word 2 4.3 Code Protection 4.3.1 Program Memory Protection 4.4 Write Protection 4.5 User ID 4.6 Device ID and Revision ID 4.7 Register Definitions: Device and Revision Register 4-3: DevID: Device ID Register Register 4-4: RevID: Revision ID Register 5.0 Resets FIGURE 5-1: Simplified Block Diagram of on-Chip Reset Circuit 5.1 Power-on Reset (POR) 5.1.1 Power-up Timer (PWRT) 5.2 Brown-out Reset (BOR) TABLE 5-1: BOR Operating Modes 5.2.1 BOR is Always On 5.2.2 BOR is Off in Sleep 5.2.3 BOR Controlled by Software FIGURE 5-2: Brown-out Situations 5.3 Register Definitions: BOR Control Register 5-1: BORCON: Brown-out Reset Control Register 5.4 Low-Power Brown-out Reset (LPBOR) 5.4.1 Enabling LPBOR 5.5 MCLR TABLE 5-2: MCLR Configuration 5.5.1 MCLR Enabled 5.5.2 MCLR Disabled 5.6 Watchdog Timer (WDT) Reset 5.7 RESET Instruction 5.8 Stack Overflow/Underflow Reset 5.9 Programming Mode Exit 5.10 Power-up Timer 5.11 Start-up Sequence FIGURE 5-3: Reset Start-up Sequence 5.12 Determining the Cause of a Reset TABLE 5-3: Reset Status Bits and Their Significance TABLE 5-4: Reset Condition for Special Registers 5.13 Power Control (PCON) Register 5.14 Register Definitions: Power Control Register 5-2: PCON: Power Control Register TABLE 5-5: Summary of Registers Associated with Resets 6.0 Oscillator Module (with Fail-Safe Clock Monitor) 6.1 Overview FIGURE 6-1: Simplified PIC® MCU Clock Source Block Diagram 6.2 Clock Source Types 6.2.1 External Clock Sources FIGURE 6-2: External Clock (EC) Mode Operation FIGURE 6-3: Quartz Crystal Operation (LP, XT or HS Mode) FIGURE 6-4: Ceramic Resonator Operation (XT or HS Mode) FIGURE 6-5: Quartz Crystal Operation (Secondary Oscillator) FIGURE 6-6: External RC Modes 6.2.2 Internal Clock Sources FIGURE 6-7: Internal Oscillator Switch Timing 6.3 Clock Switching 6.3.1 System Clock Select (SCS) Bits 6.3.2 Oscillator Start-up Timer Status (OSTS) Bit 6.3.3 Secondary Oscillator 6.3.4 Secondary Oscillator Ready (SOSCR) Bit 6.3.5 Clock Switching Before Sleep 6.4 Two-Speed Clock Start-up Mode 6.4.1 Two-Speed Start-up Mode Configuration TABLE 6-1: Oscillator Switching Delays 6.4.2 Two-Speed Start-up Sequence 6.4.3 Checking Two-Speed Clock Status FIGURE 6-8: Two-Speed Start-up 6.5 Fail-Safe Clock Monitor FIGURE 6-9: FSCM Block Diagram 6.5.1 Fail-Safe Detection 6.5.2 Fail-Safe Operation 6.5.3 Fail-Safe Condition Clearing 6.5.4 Reset or Wake-up from Sleep FIGURE 6-10: FSCM Timing Diagram 6.6 Register Definitions: Oscillator Control Register 6-1: OSCCON: Oscillator Control Register Register 6-2: OSCSTAT: Oscillator Status Register Register 6-3: OSCTUNE: Oscillator Tuning Register TABLE 6-2: Summary of Registers Associated with Clock Sources TABLE 6-3: Summary of Configuration Word with Clock Sources 7.0 Interrupts FIGURE 7-1: Interrupt Logic 7.1 Operation 7.2 Interrupt Latency FIGURE 7-2: Interrupt Latency FIGURE 7-3: INT Pin Interrupt Timing 7.3 Interrupts During Sleep 7.4 INT Pin 7.5 Automatic Context Saving 7.6 Register Definitions: Interrupt Control Register 7-1: INTCON: Interrupt Control Register Register 7-2: PIE1: Peripheral Interrupt Enable Register 1 Register 7-3: PIE2: Peripheral Interrupt Enable Register 2 Register 7-4: PIE3: Peripheral Interrupt Enable Register 3 Register 7-5: PIR1: Peripheral Interrupt Request Register 1 Register 7-6: PIR2: Peripheral Interrupt Request Register 2 Register 7-7: PIR3: Peripheral Interrupt Request Register 3 TABLE 7-1: Summary of Registers Associated with Interrupts 8.0 Power-Down Mode (Sleep) 8.1 Wake-up from Sleep 8.1.1 Wake-up Using Interrupts FIGURE 8-1: Wake-up from Sleep through Interrupt 8.2 Low-Power Sleep Mode 8.2.1 Sleep Current vs. Wake-up Time 8.2.2 Peripheral Usage in Sleep 8.3 Register Definitions: Voltage Regulator Control Register 8-1: VREGCON: Voltage Regulator Control Register(1) TABLE 8-1: Summary of Registers Associated with Power-down Mode 9.0 Watchdog Timer (WDT) FIGURE 9-1: Watchdog Timer Block Diagram 9.1 Independent Clock Source 9.2 WDT Operating Modes 9.2.1 WDT is Always On 9.2.2 WDT is Off in Sleep 9.2.3 WDT Controlled by Software TABLE 9-1: WDT Operating Modes 9.3 Time-out Period 9.4 Clearing the WDT 9.5 Operation During Sleep TABLE 9-2: WDT Clearing Conditions 9.6 Register Definitions: Watchdog Control Register 9-1: WDTCON: Watchdog Timer Control Register TABLE 9-3: Summary of Registers Associated with Watchdog Timer TABLE 9-4: Summary of Configuration Word with Watchdog Timer 10.0 Flash Program Memory Control 10.1 PMADRL and PMADRH Registers 10.1.1 PMCON1 and PMCON2 Registers 10.2 Flash Program Memory Overview TABLE 10-1: Flash Memory Organization By Device 10.2.1 Reading the Flash Program Memory FIGURE 10-1: Flash Program Memory Read Flowchart FIGURE 10-2: Flash Program Memory Read Cycle Execution EXAMPLE 10-1: Flash Program Memory Read 10.2.2 Flash Memory Unlock Sequence FIGURE 10-3: Flash Program Memory Unlock Sequence Flowchart 10.2.3 Erasing Flash Program Memory FIGURE 10-4: Flash Program Memory Erase Flowchart EXAMPLE 10-2: Erasing One Row of Program Memory 10.2.4 Writing to Flash Program Memory FIGURE 10-5: Block Writes to Flash Program Memory with 32 Write Latches FIGURE 10-6: Flash Program Memory Write Flowchart EXAMPLE 10-3: Writing to Flash Program Memory 10.3 Modifying Flash Program Memory FIGURE 10-7: Flash Program Memory Modify Flowchart 10.4 User ID, Device ID and Configuration Word Access TABLE 10-2: User ID, Device ID and Configuration Word Access (CFGS = 1) EXAMPLE 10-4: Configuration Word and Device ID Access 10.5 Write Verify FIGURE 10-8: Flash Program Memory Verify Flowchart 10.6 Register Definitions: Flash Program Memory Control Register 10-1: PMDATL: Program Memory Data Low Byte Register Register 10-2: PMDATH: Program Memory Data High Byte Register Register 10-3: PMADRL: Program Memory Address Low Byte Register Register 10-4: PMADRH: Program Memory Address High Byte Register Register 10-5: PMCON1: Program Memory Control 1 Register Register 10-6: PMCON2: Program Memory Control 2 Register TABLE 10-3: Summary of Registers Associated with Flash Program Memory TABLE 10-4: Summary of Configuration Word with Flash Program Memory 11.0 I/O Ports TABLE 11-1: Port Availability per Device FIGURE 11-1: Generic I/O Port Operation 11.1 PORTA Registers 11.1.1 Data Register 11.1.2 Direction Control 11.1.3 Open-Drain Control 11.1.4 Slew Rate Control 11.1.5 Input Threshold Control 11.1.6 Analog Control EXAMPLE 11-1: Initializing PORTA 11.1.7 PORTA Functions and Output Priorities 11.2 Register Definitions: PORTA Register 11-1: PORTA: PORTA Register Register 11-2: TRISA: PORTA Tri-State Register Register 11-3: LATA: PORTA Data Latch Register Register 11-4: ANSELA: PORTA Analog Select Register Register 11-5: WPUA: Weak Pull-up PORTA Register(1,2) Register 11-6: ODCONA: PORTA Open-Drain Control Register Register 11-7: SLRCONA: PORTA Slew Rate Control Register Register 11-8: INLVLA: PORTA Input Level Control Register TABLE 11-2: Summary of Registers Associated with PORTA TABLE 11-3: Summary of Configuration Word with PORTA 11.3 PORTB Registers 11.3.1 Data Register 11.3.2 Direction Control 11.3.3 Open-Drain Control 11.3.4 Slew Rate Control 11.3.5 Input Threshold Control 11.3.6 Analog Control 11.3.7 PORTB Functions and Output Priorities 11.4 Register Definitions: PORTB Register 11-9: PORTB: PORTB Register Register 11-10: TRISB: PORTB Tri-State Register Register 11-11: LATB: PORTB Data Latch Register Register 11-12: ANSELB: PORTB Analog Select Register Register 11-13: WPUB: Weak Pull-up PORTB Register(1,2) Register 11-14: ODCONB: PORTB Open-Drain Control Register Register 11-15: SLRCONB: PORTB Slew Rate Control Register Register 11-16: INLVLB: PORTB Input Level Control Register TABLE 11-4: Summary of Registers Associated with PORTB 11.5 PORTC Registers 11.5.1 Data Register 11.5.2 Direction Control 11.5.3 Input Threshold Control 11.5.4 Open-Drain Control 11.5.5 Slew Rate Control 11.5.6 Analog Control 11.5.7 PORTC Functions and Output Priorities 11.6 Register Definitions: PORTC Register 11-17: PORTC: PORTC Register Register 11-18: TRISC: PORTC Tri-State Register Register 11-19: LATC: PORTC Data Latch Register Register 11-20: ANSELC: PORTC Analog Select Register Register 11-21: WPUC: Weak Pull-up PORTC Register(1,2) Register 11-22: ODCONC: PORTC Open-Drain Control Register Register 11-23: SLRCONC: PORTC Slew Rate Control Register Register 11-24: INLVLC: PORTC Input Level Control Register TABLE 11-5: Summary of Registers Associated with PORTC 11.7 PORTD Registers (PIC16(L)F1717/9 only) 11.7.1 Data Register 11.7.2 Direction Control 11.7.3 Input Threshold Control 11.7.4 Open-Drain Control 11.7.5 Slew Rate Control 11.7.6 Analog Control 11.7.7 PORTD Functions and Output Priorities 11.8 Register Definitions: PORTD Register 11-25: PORTD: PORTD Register Register 11-26: TRISD: PORTD Tri-State Register Register 11-27: LATD: PORTD Data Latch Register Register 11-28: ANSELD: PORTD Analog Select Register Register 11-29: WPUD: Weak Pull-up PORTD Register(1,2) Register 11-30: ODCOND: PORTD Open-Drain Control Register Register 11-31: SLRCOND: PORTD Slew Rate Control Register Register 11-32: INLVLD: PORTD Input Level Control Register TABLE 11-6: Summary of Registers Associated with PORTD 11.9 PORTE Registers 11.9.1 Data Register (RE<2:0> PIC16(L)F1717/9 only) 11.9.2 Direction Control (TRISE<2:0> PIC16(L)F1717/9 only) 11.9.3 Input Threshold Control (PIC16(L)F1717/9 only) 11.9.4 Open-Drain Control (PIC16(L)F1717/9 only) 11.9.5 Slew Rate Control (PIC16(L)F1717/9 only) 11.9.6 Analog Control (PIC16(L)F1717/9 only) 11.9.7 PORTE Functions and Output Priorities (PIC16(L)F1717/9 only) 11.10 Register Definitions: PORTE Register 11-33: PORTE: PORTE Register Register 11-34: TRISE: PORTE Tri-State Register Register 11-35: LATE: PORTE Data Latch Register(1) Register 11-36: ANSELE: PORTE Analog Select Register(2) Register 11-37: WPUE: Weak Pull-Up PORTE Register(1,2) Register 11-38: ODCONE: PORTE Open-Drain Control Register(1) Register 11-39: SLRCONE: PORTE Slew Rate Control Register(1) Register 11-40: INLVLE: PORTE Input Level Control Register(1) TABLE 11-7: Summary of Registers Associated with PORTE 12.0 Peripheral Pin Select (PPS) Module 12.1 PPS Inputs 12.2 PPS Outputs FIGURE 12-1: Simplified PPS Block Diagram 12.3 Bidirectional Pins 12.4 PPS Lock EXAMPLE 12-1: PPS Lock/Unlock sequence 12.5 PPS Permanent Lock 12.6 Operation During Sleep 12.7 Effects of a Reset 12.8 Register Definitions: PPS Input Selection Register 12-1: xxxPPS: Peripheral xxx Input Selection TABLE 12-1: Available Ports for Input by Peripheral Register 12-2: RxyPPS: Pin Rxy Output Source Selection Register TABLE 12-2: Available Ports for Output by Peripheral (1) Register 12-3: PPSLOCK: PPS Lock Register TABLE 12-3: Summary of Registers Associated with the PPS Module 13.0 Interrupt-on-Change 13.1 Enabling the Module 13.2 Individual Pin Configuration 13.3 Interrupt Flags 13.4 Clearing Interrupt Flags EXAMPLE 13-1: Clearing Interrupt Flags (PORTA Example) 13.5 Operation in Sleep FIGURE 13-1: Interrupt-on-Change Block Diagram (PORTA Example) 13.6 Register Definitions: Interrupt-on-Change Control Register 13-1: IOCAP: Interrupt-on-Change PORTA Positive Edge Register Register 13-2: IOCAN: Interrupt-on-Change PORTA Negative Edge Register Register 13-3: IOCAF: Interrupt-on-Change PORTA Flag Register Register 13-4: IOCBP: Interrupt-on-Change PORTB Positive Edge Register Register 13-5: IOCBN: Interrupt-on-Change PORTB Negative Edge Register Register 13-6: IOCBF: Interrupt-on-Change PORTB Flag Register Register 13-7: IOCCP: Interrupt-on-Change PORTC Positive Edge Register Register 13-8: IOCCN: Interrupt-on-Change PORTC Negative Edge Register Register 13-9: IOCCF: Interrupt-on-Change PORTC Flag Register Register 13-10: IOCEP: Interrupt-on-Change PORTe Positive Edge Register Register 13-11: IOCEN: Interrupt-on-Change PORTE Negative Edge Register Register 13-12: IOCEF: Interrupt-on-Change PORTE Flag Register TABLE 13-1: Summary of Registers Associated with Interrupt-on-Change 14.0 Fixed Voltage Reference (FVR) 14.1 Independent Gain Amplifiers 14.2 FVR Stabilization Period FIGURE 14-1: Voltage Reference Block Diagram TABLE 14-1: Peripherals Requiring the Fixed Voltage Reference (FVR) 14.3 Register Definitions: FVR Control Register 14-1: FVRCON: Fixed Voltage Reference Control Register TABLE 14-2: Summary of Registers Associated with Fixed Voltage Reference 15.0 Temperature Indicator Module 15.1 Circuit Operation EQUATION 15-1: Vout Ranges FIGURE 15-1: Temperature Circuit Diagram 15.2 Minimum Operating Vdd TABLE 15-1: Recommended Vdd vs. Range 15.3 Temperature Output 15.4 ADC Acquisition Time TABLE 15-2: Summary of Registers Associated with the Temperature Indicator 16.0 Comparator Module 16.1 Comparator Overview TABLE 16-1: Available Comparators FIGURE 16-1: Single Comparator FIGURE 16-2: Comparator Module Simplified Block Diagram 16.2 Comparator Control 16.2.1 Comparator Enable 16.2.2 Comparator Output Selection 16.2.3 Comparator Output Polarity TABLE 16-2: Comparator Output State vs. Input Conditions 16.2.4 Comparator Speed/Power Selection 16.3 Comparator Hysteresis 16.4 Timer1 Gate Operation 16.4.1 Comparator Output Synchronization 16.5 Comparator Interrupt 16.6 Comparator Positive Input Selection 16.7 Comparator Negative Input Selection 16.8 Comparator Response Time 16.9 Zero Latency Filter FIGURE 16-3: Comparator Zero Latency Filter Operation 16.10 Analog Input Connection Considerations FIGURE 16-4: Analog Input Model 16.11 Register Definitions: Comparator Control Register 16-1: CMxCON0: Comparator Cx Control Register 0 Register 16-2: CMxCON1: Comparator Cx Control Register 1 Register 16-3: CMOUT: Comparator Output Register TABLE 16-3: Summary of Registers Associated with Comparator Module 17.0 Pulse Width Modulation (PWM) FIGURE 17-1: Simplified PWM Block Diagram FIGURE 17-2: PWM Output 17.1 PWMx Pin Configuration 17.1.1 Fundamental Operation 17.1.2 PWM Output Polarity 17.1.3 PWM Period EQUATION 17-1: PWM Period 17.1.4 PWM Duty Cycle EQUATION 17-2: Pulse Width EQUATION 17-3: Duty Cycle Ratio 17.1.5 PWM Resolution EQUATION 17-4: PWM Resolution TABLE 17-1: Example PWM Frequencies and Resolutions (Fosc = 20 MHz) TABLE 17-2: Example PWM Frequencies and Resolutions (Fosc = 8 MHz) 17.1.6 Operation in Sleep Mode 17.1.7 Changes in System Clock Frequency 17.1.8 Effects of Reset 17.1.9 Setup for PWM Operation Using PWMx Pins 17.1.10 Setup for PWM Operation to Other Device Peripherals 17.2 Register Definitions: PWM Control Register 17-1: PWMxCON: PWM Control Register Register 17-2: PWMXDCH: PWM Duty Cycle High Bits Register 17-3: PWMxDCL: PWM Duty Cycle Low Bits TABLE 17-3: Summary of Registers Associated with PWM 18.0 Complementary Output Generator (COG) Module 18.1 Fundamental Operation 18.1.1 Steered PWM Modes 18.1.2 Full-Bridge Modes FIGURE 18-1: Example of Full-Bridge Application 18.1.3 Half-Bridge Mode 18.1.4 Push-Pull Mode 18.1.5 Event driven PWM (all modes) FIGURE 18-2: Simplified COG Block Diagram (Steered PWM Mode, GxMD = 0) FIGURE 18-3: Simplified COG Block Diagram (Synchronous Steered PWM Mode, GxMD = 1) FIGURE 18-4: Simplified COG Block Diagram (Full-Bridge Modes, Forward: GxMD = 2, Reverse: GxMD = 3) FIGURE 18-5: Simplified COG Block Diagram (Half-Bridge Mode, GxMD = 4) FIGURE 18-6: Simplified COG Block Diagram (Push-Pull Mode, GxMD = 5) FIGURE 18-7: COG (Rising/Falling) Input Block FIGURE 18-8: COG (Rising/Falling) Dead-band block FIGURE 18-9: Typical Half-Bridge mode COG Operation with CCP1 FIGURE 18-10: Half-Bridge Mode COG operation with CCP1 and Phase Delay FIGURE 18-11: Push-Pull mode COG operation with CCP1 FIGURE 18-12: Full-Bridge Forward mode COG operation with CCP1 FIGURE 18-13: Full-Bridge Mode COG Operation with CCP1 and Direction Change 18.2 Clock Sources 18.3 Selectable Event Sources 18.3.1 Edge vs. Level Sensing FIGURE 18-14: Edge Vs Level Sense 18.3.2 Rising Event 18.3.3 Falling Event 18.4 Output Control 18.4.1 Output Enables TABLE 18-1: Pin Output States 18.4.2 Polarity Control 18.5 Dead-Band Control 18.5.1 Asynchronous Delay Chain Dead-Band Delay 18.5.2 Synchronous Counter Dead-Band Delay 18.5.3 Synchronous Counter Dead-band Time Uncertainty 18.5.4 Rising Event Dead band 18.5.5 Falling event Dead band 18.5.6 Dead-band Overlap 18.6 Blanking Control 18.6.1 Falling Event Blanking of Rising Event Inputs 18.6.2 Rising Event Blanking of Falling Event Inputs 18.6.3 Blanking Time Uncertainty 18.7 Phase Delay 18.7.1 Cumulative Uncertainty EQUATION 18-1: Phase, Dead-Band, and Blanking Time Calculation EXAMPLE 18-1: Timer Uncertainty 18.8 Auto-shutdown Control 18.8.1 Shutdown 18.8.2 PIN Override Levels 18.8.3 Auto-Shutdown Restart FIGURE 18-15: Auto-Shutdown Waveform – CCP1 as Rising and Falling Event Input Source 18.9 Buffer Updates 18.10 Input and Output Pin Selection 18.11 Operation During Sleep 18.12 Configuring the COG 18.13 Register Definitions: COG Control Register 18-1: COGxCON0: COG Control Register 0 Register 18-2: COGxCON1: COG Control Register 1 Register 18-3: COGxRIS: COG Rising Event Input Selection Register Register 18-4: COGxRSIM: COG Rising Event Source Input MOde Register Register 18-5: COGxFIS: COG Falling Event Input Selection Register Register 18-6: COGxFSIM: COG Falling Event Source Input Mode Register Register 18-7: COGXASD0: COG Auto-Shutdown Control Register 0 Register 18-8: COGXASD1: COG Auto-Shutdown Control Register 1 Register 18-9: COGXSTR: COG Steering Control Register 1 Register 18-10: COGXDBR: COG Rising Event Dead-Band Count Register Register 18-11: COGXDBF: COG Falling Event Dead-Band Count Register Register 18-12: COGXBLKR: COG Rising Event Blanking Count Register Register 18-13: COGXBLKF: COG Falling Event Blanking Count Register Register 18-14: COGXPHR: COG Rising Edge Phase Delay Count Register Register 18-15: COGXPHF: COG Falling Edge Phase Delay Count Register TABLE 18-2: Summary of Registers Associated with COG 19.0 Configurable Logic Cell (CLC) FIGURE 19-1: CLCx Simplified Block Diagram 19.1 CLCx Setup 19.1.1 Data Selection TABLE 19-1: CLCx Data Input Selection 19.1.2 Data Gating TABLE 19-2: Data Gating Logic 19.1.3 Logic Function 19.1.4 Output Polarity 19.1.5 CLCx Setup Steps 19.2 CLCx Interrupts 19.3 Output Mirror Copies 19.4 Effects of a Reset 19.5 Operation During Sleep FIGURE 19-2: Input Data Selection and Gating FIGURE 19-3: Programmable Logic Functions 19.6 Register Definitions: CLC Control Register 19-1: CLCxCON: Configurable Logic Cell Control Register Register 19-2: CLCxPOL: Signal Polarity Control Register Register 19-3: CLCxSEL0: Generic CLCx Data 1 Select Register Register 19-4: CLCxSEL1: Generic CLCx Data 2 Select Register Register 19-5: CLCxSEL2: Generic CLCx Data 3 Select Register Register 19-6: CLCxSEL3: Generic CLCx Data 4 Select Register Register 19-7: CLCxGLS0: Gate 1 Logic Select Register Register 19-8: CLCxGLS1: Gate 2 Logic Select Register Register 19-9: CLCxGLS2: Gate 3 Logic Select Register Register 19-10: CLCxGLS3: Gate 4 Logic Select Register Register 19-11: CLCDATA: CLC Data Output TABLE 19-3: Summary of Registers Associated with CLCx 20.0 Numerically Controlled Oscillator (NCO) Module 20.1 NCOx Operation 20.1.1 NCOx Clock Sources 20.1.2 Accumulator 20.1.3 Adder 20.1.4 Increment Registers EQUATION 20-1: FIGURE 20-1: Numerically Controlled Oscillator (NCOx) Module Simplified Block Diagram 20.2 Fixed Duty Cycle (FDC) Mode 20.3 Pulse Frequency (PF) Mode 20.3.1 Output Pulse Width Control 20.4 Output Polarity Control 20.5 Interrupts 20.6 Effects of a Reset 20.7 Operation in Sleep FIGURE 20-2: NCO – Fixed Duty Cycle (FDC) and Pulse Frequency Mode (PFM) Output Operation Diagram 20.8 Register Definitions: NCOx Control Registers Register 20-1: NCOxCON: NCOx Control Register Register 20-2: NCOxCLK: NCOx Input Clock Control Register Register 20-3: NCOxACCL: NCOx Accumulator Register – Low Byte Register 20-4: NCOxACCH: NCOx Accumulator Register – High Byte Register 20-5: NCOxACCU: NCOx Accumulator Register – Upper Byte Register 20-6: NCOxINCL: NCOx Increment Register – Low Byte(1) Register 20-7: NCOxINCH: NCOx Increment Register – High Byte(1) Register 20-8: NCOxINCU: NCOx Increment Register – Upper Byte(1) TABLE 20-1: Summary of Registers Associated with NCOx 21.0 Analog-to-Digital Converter (ADC) Module FIGURE 21-1: ADC Block Diagram 21.1 ADC Configuration 21.1.1 Port Configuration 21.1.2 Channel Selection 21.1.3 ADC Voltage Reference 21.1.4 Conversion Clock TABLE 21-1: ADC Clock Period (Tad) vs. Device Operating Frequencies FIGURE 21-2: Analog-to-Digital Conversion Tad Cycles 21.1.5 Interrupts 21.1.6 Result Formatting FIGURE 21-3: 10-Bit ADC Conversion Result Format 21.2 ADC Operation 21.2.1 Starting a Conversion 21.2.2 Completion of a Conversion 21.2.3 Terminating a Conversion 21.2.4 ADC Operation During Sleep 21.2.5 Auto-Conversion Trigger TABLE 21-2: Auto-Conversion Sources 21.2.6 ADC Conversion Procedure EXAMPLE 21-1: ADC Conversion 21.3 Register Definitions: ADC Control Register 21-1: ADCON0: ADC Control Register 0 Register 21-2: ADCON1: ADC Control Register 1 Register 21-3: ADCON2: ADC Control Register 2 Register 21-4: ADRESH: ADC Result Register High (ADRESH) ADFM = 0 Register 21-5: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0 Register 21-6: ADRESH: ADC Result Register High (ADRESH) ADFM = 1 Register 21-7: ADRESL: ADC Result Register Low (ADRESL) ADFM = 1 21.4 ADC Acquisition Requirements EQUATION 21-1: Acquisition Time Example FIGURE 21-4: Analog Input Model FIGURE 21-5: ADC Transfer Function TABLE 21-3: Summary of Registers Associated with ADC 22.0 Operational Amplifier (OPA) Modules FIGURE 22-1: OPAx Module Block Diagram 22.1 OPA Module Performance 22.1.1 OPA Module Control 22.1.2 Unity Gain Mode 22.2 Effects of Reset 22.3 Register Definitions: Op Amp Control Register 22-1: OPAxCON: Operational Amplifiers (OPAx) Control Registers TABLE 22-1: Summary of Registers Associated with Op Amps 23.0 8-Bit Digital-to-Analog Converter (DAC1) Module 23.1 Output Voltage Selection EQUATION 23-1: DAC Output Voltage 23.2 Ratiometric Output Level 23.3 DAC Voltage Reference Output FIGURE 23-1: Digital-to-Analog Converter Block Diagram FIGURE 23-2: Voltage Reference Output Buffer Example 23.4 Operation During Sleep 23.5 Effects of a Reset 23.6 Register Definitions: DAC Control Register 23-1: DAC1CON0: DAC1 Control Register 0 Register 23-2: DAC1CON1: DAC1 Control Register 1 TABLE 23-1: Summary of Registers Associated with the DAC1 Module 24.0 5-Bit Digital-to-Analog Converter (DAC2) Module 24.1 Output Voltage Selection EQUATION 24-1: DAC Output Voltage 24.2 Ratiometric Output Level 24.3 DAC Voltage Reference Output FIGURE 24-1: Digital-to-Analog Converter Block Diagram FIGURE 24-2: Voltage Reference Output Buffer Example 24.4 Operation During Sleep 24.5 Effects of a Reset 24.6 Register Definitions: DAC Control Register 24-1: DAC2CON0: Voltage Reference Control Register 0 Register 24-2: DAC2CON1: Voltage Reference Control Register 1 TABLE 24-1: Summary of Registers Associated with the DAC2 Module 25.0 Zero-Cross Detection (ZCD) Module 25.1 External Resistor Selection EQUATION 25-1: External Resistor FIGURE 25-1: External Voltage FIGURE 25-2: Simplified ZCD Block Diagram 25.2 ZCD Logic Output 25.3 ZCD Logic Polarity 25.4 ZCD Interrupts 25.5 Correcting for Zcpinv Offset 25.5.1 Correction by AC Coupling EQUATION 25-2: R-C Calculations EQUATION 25-3: R-C Calculations Example 25.5.2 Correction by offset current EQUATION 25-4: ZCD Event Offset EQUATION 25-5: ZCD Pull-up/down EQUATION 25-6: 25.6 Handling Vpeak variations EQUATION 25-7: Series R for V Range 25.7 Operation During Sleep 25.8 Effects of a Reset 25.9 Register Definitions: ZCD Control TABLE 25-1: Register 25-1: ZCDxCON: Zero-Cross Detection Control Register TABLE 25-2: Summary of Registers Associated with the ZCD Module TABLE 25-3: Summary of Configuration Word with the ZCD Module 26.0 Timer0 Module 26.1 Timer0 Operation 26.1.1 8-Bit Timer Mode 26.1.2 8-Bit Counter Mode FIGURE 26-1: Block Diagram of the Timer0 26.1.3 Software Programmable Prescaler 26.1.4 Timer0 Interrupt 26.1.5 8-Bit Counter Mode Synchronization 26.1.6 Operation During Sleep 26.2 Register Definitions: Option Register Register 26-1: OPTION_REG: OPTION Register TABLE 26-1: Summary of Registers Associated with Timer0 27.0 Timer1 Module with Gate Control FIGURE 27-1: Timer1 Block Diagram 27.1 Timer1 Operation TABLE 27-1: Timer1 Enable Selections 27.2 Clock Source Selection 27.2.1 Internal Clock Source 27.2.2 External Clock Source TABLE 27-2: Clock Source Selections 27.3 Timer1 Prescaler 27.4 Timer1 (Secondary) Oscillator 27.5 Timer1 Operation in Asynchronous Counter Mode 27.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode 27.6 Timer1 Gate 27.6.1 Timer1 Gate Enable TABLE 27-3: Timer1 Gate Enable Selections 27.6.2 Timer1 Gate Source Selection TABLE 27-4: Timer1 Gate Sources 27.6.3 Timer1 Gate Toggle Mode 27.6.4 Timer1 Gate Single-Pulse Mode 27.6.5 Timer1 Gate Value Status 27.6.6 Timer1 Gate Event Interrupt 27.7 Timer1 Interrupt 27.8 Timer1 Operation During Sleep 27.9 CCP Capture/Compare Time Base 27.10 CCP Auto-Conversion Trigger FIGURE 27-2: Timer1 Incrementing Edge FIGURE 27-3: Timer1 Gate Enable Mode FIGURE 27-4: Timer1 Gate Toggle Mode FIGURE 27-5: Timer1 Gate Single-Pulse Mode FIGURE 27-6: Timer1 Gate Single-Pulse and Toggle Combined Mode 27.11 Register Definitions: Timer1 Control Register 27-1: T1CON: Timer1 Control Register Register 27-2: T1GCON: Timer1 Gate Control Register TABLE 27-5: Summary of Registers Associated with Timer1 28.0 Timer2/4/6 Module FIGURE 28-1: Timer2 Block Diagram 28.1 Timer2 Operation 28.2 Timer2 Interrupt 28.3 Timer2 Output 28.4 Timer2 Operation During Sleep 28.5 Register Definitions: Timer2 Control Register 28-1: T2CON: Timer2 Control Register TABLE 28-1: Summary of Registers Associated with Timer2 28.6 CCP/PWM Clock Selection 28.7 Register Definitions: CCP/PWM Timers Control Register 28-2: CCPTMRS: PWM Timer Selection Control Register 0 29.0 Capture/Compare/PWM Modules 29.1 Capture Mode 29.1.1 CCP Pin Configuration FIGURE 29-1: Capture Mode Operation Block Diagram 29.1.2 Timer1 Mode Resource 29.1.3 Software Interrupt Mode 29.1.4 CCP Prescaler EXAMPLE 29-1: Changing between Capture Prescalers 29.1.5 Capture During Sleep 29.2 Compare Mode FIGURE 29-2: Compare Mode Operation Block Diagram 29.2.1 CCPx Pin Configuration 29.2.2 Timer1 Mode Resource 29.2.3 Software Interrupt Mode 29.2.4 Auto-Conversion Trigger 29.2.5 Compare During Sleep 29.3 PWM Overview 29.3.1 Standard PWM Operation FIGURE 29-3: CCP PWM Output Signal FIGURE 29-4: Simplified PWM Block Diagram 29.3.2 Setup for PWM Operation 29.3.3 Timer2 Timer Resource 29.3.4 PWM Period EQUATION 29-1: PWM Period 29.3.5 PWM Duty Cycle EQUATION 29-2: Pulse Width EQUATION 29-3: Duty Cycle Ratio 29.3.6 PWM Resolution EQUATION 29-4: PWM Resolution TABLE 29-1: Example PWM Frequencies and Resolutions (Fosc = 20 MHz) TABLE 29-2: Example PWM Frequencies and Resolutions (Fosc = 8 MHz) 29.3.7 Operation in Sleep Mode 29.3.8 Changes in System Clock Frequency 29.3.9 Effects of Reset TABLE 29-3: Summary of Registers Associated with CCP 29.4 Register Definitions: CCP Control Register 29-1: CCPXCON: CCPx Control Register 30.0 Master Synchronous Serial Port (MSSP) Module 30.1 MSSP Module Overview FIGURE 30-1: MSSP Block Diagram (SPI Mode) FIGURE 30-2: MSSP Block Diagram (I2C Master mode) FIGURE 30-3: MSSP Block Diagram (I2C Slave mode) 30.2 SPI Mode Overview FIGURE 30-4: SPI Master and Multiple Slave Connection 30.2.1 SPI Mode Registers 30.2.2 SPI Mode Operation FIGURE 30-5: SPI Master/Slave Connection 30.2.3 SPI Master Mode FIGURE 30-6: SPI Mode Waveform (Master Mode) 30.2.4 SPI Slave Mode 30.2.5 Slave Select Synchronization FIGURE 30-7: SPI Daisy-Chain Connection FIGURE 30-8: Slave Select Synchronous Waveform FIGURE 30-9: SPI Mode Waveform (Slave Mode with CKE = 0) FIGURE 30-10: SPI Mode Waveform (Slave Mode with CKE = 1) 30.2.6 SPI Operation in Sleep Mode TABLE 30-1: Summary of Registers Associated with SPI Operation 30.3 I2C Mode Overview FIGURE 30-11: I2C Master/ Slave Connection 30.3.1 Clock Stretching 30.3.2 Arbitration 30.4 I2C Mode Operation 30.4.1 Byte Format 30.4.2 Definition of I2C Terminology 30.4.3 SDA and SCL Pins 30.4.4 SDA Hold Time TABLE 30-2: I2C Bus Terms 30.4.5 Start Condition 30.4.6 Stop Condition 30.4.7 Restart Condition 30.4.8 Start/Stop Condition Interrupt Masking FIGURE 30-12: I2C Start and Stop Conditions FIGURE 30-13: I2C Restart Condition 30.4.9 Acknowledge Sequence 30.5 I2C Slave Mode Operation 30.5.1 Slave Mode Addresses 30.5.2 Slave Reception FIGURE 30-14: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0) FIGURE 30-15: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 30-16: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1) FIGURE 30-17: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1) 30.5.3 Slave Transmission FIGURE 30-18: I2C Slave, 7-Bit Address, Transmission (AHEN = 0) FIGURE 30-19: I2C Slave, 7-Bit Address, Transmission (AHEN = 1) 30.5.4 Slave Mode 10-Bit Address Reception 30.5.5 10-Bit Addressing with Address or Data Hold FIGURE 30-20: I2C Slave, 10-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 30-21: I2C Slave, 10-Bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 0) FIGURE 30-22: I2C Slave, 10-Bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0) 30.5.6 Clock Stretching 30.5.7 Clock Synchronization and the CKP Bit FIGURE 30-23: Clock Synchronization Timing 30.5.8 General Call Address Support FIGURE 30-24: Slave Mode General Call Address Sequence 30.5.9 SSP Mask Register 30.6 I2C Master Mode 30.6.1 I2C Master Mode Operation 30.6.2 Clock Arbitration FIGURE 30-25: Baud Rate Generator Timing with Clock Arbitration 30.6.3 WCOL Status Flag 30.6.4 I2C Master Mode Start Condition Timing FIGURE 30-26: First Start Bit Timing 30.6.5 I2C Master Mode Repeated Start Condition Timing FIGURE 30-27: Repeated Start Condition Waveform 30.6.6 I2C Master Mode Transmission FIGURE 30-28: I2C Master Mode Waveform (Transmission, 7 or 10-Bit Address) 30.6.7 I2C Master Mode Reception FIGURE 30-29: I2C Master Mode Waveform (Reception, 7-bit Address) 30.6.8 Acknowledge Sequence Timing 30.6.9 Stop Condition Timing FIGURE 30-30: Acknowledge Sequence Waveform FIGURE 30-31: Stop Condition Receive or Transmit Mode 30.6.10 Sleep Operation 30.6.11 Effects of a Reset 30.6.12 Multi-Master Mode 30.6.13 Multi-Master Communication, Bus Collision and Bus Arbitration FIGURE 30-32: Bus Collision Timing for Transmit and Acknowledge FIGURE 30-33: Bus Collision During Start Condition (SDA Only) FIGURE 30-34: Bus Collision During Start Condition (SCL = 0) FIGURE 30-35: BRG Reset due to SDA Arbitration During Start Condition FIGURE 30-36: Bus Collision During a Repeated Start Condition (Case 1) FIGURE 30-37: Bus Collision During Repeated Start Condition (Case 2) FIGURE 30-38: Bus Collision During a Stop Condition (Case 1) FIGURE 30-39: Bus Collision during a Stop Condition (Case 2) TABLE 30-3: Summary of Registers Associated with I2C Operation 30.7 Baud Rate Generator FIGURE 30-40: Baud Rate Generator Block Diagram TABLE 30-4: MSSP Clock Rate w/BRG 30.8 Register Definitions: MSSP Control Register 30-1: SSP1STAT: SSP STATUS Register Register 30-2: SSP1CON1: SSP Control Register 1 Register 30-3: SSP1CON2: SSP Control Register 2(1) Register 30-4: SSP1CON3: SSP Control Register 3 Register 30-5: SSP1MSK: SSP Mask Register Register 30-6: SSP1ADD: MSSP Address and Baud Rate Register (I2C Mode) 31.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) FIGURE 31-1: EUSART Transmit Block Diagram FIGURE 31-2: EUSART Receive Block Diagram 31.1 EUSART Asynchronous Mode 31.1.1 EUSART Asynchronous Transmitter FIGURE 31-3: Asynchronous Transmission FIGURE 31-4: Asynchronous Transmission (Back-to-Back) TABLE 31-1: Summary of Registers Associated with Asynchronous Transmission 31.1.2 EUSART Asynchronous Receiver FIGURE 31-5: Asynchronous Reception TABLE 31-2: Summary of Registers Associated with Asynchronous Reception 31.2 Clock Accuracy with Asynchronous Operation 31.3 Register Definitions: EUSART Control Register 31-1: TX1STA: Transmit Status and Control Register Register 31-2: RC1STA: Receive Status and Control Register Register 31-3: BAUD1CON: Baud Rate Control Register 31.4 EUSART Baud Rate Generator (BRG) EXAMPLE 31-1: Calculating Baud Rate Error TABLE 31-3: Baud Rate Formulas TABLE 31-4: Summary of Registers Associated with the Baud Rate Generator TABLE 31-5: BAUD Rates for Asynchronous Modes 31.4.1 Auto-Baud Detect TABLE 31-6: BRG Counter Clock Rates FIGURE 31-6: Automatic Baud Rate Calibration 31.4.2 Auto-Baud Overflow 31.4.3 Auto-Wake-up on Break FIGURE 31-7: Auto-Wake-up Bit (WUE) Timing During Normal Operation FIGURE 31-8: Auto-Wake-up Bit (WUE) Timings During Sleep 31.4.4 Break Character Sequence 31.4.5 Receiving a Break Character FIGURE 31-9: Send Break Character Sequence 31.5 EUSART Synchronous Mode 31.5.1 Synchronous Master Mode FIGURE 31-10: Synchronous Transmission FIGURE 31-11: Synchronous Transmission (through TXEN) TABLE 31-7: Summary of Registers Associated with Synchronous Master Transmission FIGURE 31-12: Synchronous Reception (Master Mode, SREN) TABLE 31-8: Summary of Registers Associated with Synchronous Master Reception 31.5.2 Synchronous Slave Mode TABLE 31-9: Summary of Registers Associated with Synchronous Slave Transmission TABLE 31-10: Summary of Registers Associated with Synchronous Slave Reception 31.6 EUSART Operation During Sleep 31.6.1 Synchronous Receive During Sleep 31.6.2 Synchronous Transmit During Sleep 32.0 In-Circuit Serial Programming (ICSP™) 32.1 High-Voltage Programming Entry Mode 32.2 Low-Voltage Programming Entry Mode 32.3 Common Programming Interfaces FIGURE 32-1: ICD RJ-11 Style Connector Interface FIGURE 32-2: PICkit™ Programmer Style Connector Interface FIGURE 32-3: Typical Connection for ICSP™ Programming 33.0 Instruction Set Summary 33.1 Read-Modify-Write Operations TABLE 33-1: Opcode Field Descriptions TABLE 33-2: Abbreviation Descriptions FIGURE 33-1: General Format for Instructions TABLE 33-3: PIC16(L)F1717/8/9 Instruction Set 33.2 Instruction Descriptions 34.0 Electrical Specifications 34.1 Absolute Maximum Ratings(†) 34.2 Standard Operating Conditions FIGURE 34-1: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC16F1717/8/9 Only FIGURE 34-2: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC16LF1717/8/9 Only 34.3 DC Characteristics TABLE 34-1: Supply Voltage FIGURE 34-3: POR and POR Rearm with Slow Rising Vdd TABLE 34-2: Supply Current (Idd)(1,2) TABLE 34-3: Power-down Currents (Ipd)(1,2) TABLE 34-4: I/O Ports TABLE 34-5: Memory Programming Specifications TABLE 34-6: Thermal Characteristics 34.4 AC Characteristics FIGURE 34-4: Load Conditions FIGURE 34-5: Clock Timing TABLE 34-7: Clock Oscillator Timing Requirements TABLE 34-8: Oscillator Parameters FIGURE 34-6: HFINTOSC Frequency Accuracy over Device Vdd and Temperature TABLE 34-9: PLL Clock Timing Specifications FIGURE 34-7: CLKOUT and I/O Timing TABLE 34-10: CLKOUT and I/O Timing Parameters FIGURE 34-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing TABLE 34-11: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Parameters FIGURE 34-9: Timer0 and Timer1 External Clock Timings FIGURE 34-10: Brown-out Reset Timing and Characteristics TABLE 34-12: Timer0 and Timer1 External Clock Requirements FIGURE 34-11: Capture/Compare/PWM Timings (CCP) TABLE 34-13: Capture/Compare/PWM Requirements (CCP) FIGURE 34-12: CLC Propagation Timing TABLE 34-14: Configuration Logic Cell (CLC) Characteristics TABLE 34-15: Analog-to-Digital Converter (ADC) Characteristics(1,2,3,4) TABLE 34-16: ADC Conversion Requirements FIGURE 34-13: ADC Conversion Timing (ADC Clock Fosc-Based) FIGURE 34-14: ADC Conversion Timing (ADC Clock from FRC) TABLE 34-17: Operational Amplifier (OPA) TABLE 34-18: Comparator Specifications TABLE 34-19: 8-Bit Digital-to-Analog Converter (DAC) Specifications TABLE 34-20: 5-Bit Digital-to-Analog Converter (DAC) Specifications TABLE 34-21: Zero-Cross Pin Specifications FIGURE 34-15: EUSART Synchronous Transmission (Master/Slave) Timing TABLE 34-22: EUSART Synchronous Transmission Requirements FIGURE 34-16: EUSART Synchronous Receive (Master/Slave) Timing TABLE 34-23: EUSART Synchronous Receive Requirements FIGURE 34-17: SPI Master Mode Timing (CKE = 0, SMP = 0) FIGURE 34-18: SPI Master Mode Timing (CKE = 1, SMP = 1) FIGURE 34-19: SPI Slave Mode Timing (CKE = 0) FIGURE 34-20: SPI Slave Mode Timing (CKE = 1) TABLE 34-24: SPI Mode Requirements FIGURE 34-21: I2C Bus Start/Stop Bits Timing TABLE 34-25: I2C Bus Start/Stop Bits Requirements FIGURE 34-22: I2C Bus Data Timing TABLE 34-26: I2C Bus Data Requirements 35.0 DC and AC Characteristics Graphs and Charts 36.0 Development Support 36.1 MPLAB X Integrated Development Environment Software 36.2 MPLAB XC Compilers 36.3 MPASM Assembler 36.4 MPLINK Object Linker/ MPLIB Object Librarian 36.5 MPLAB Assembler, Linker and Librarian for Various Device Families 36.6 MPLAB X SIM Software Simulator 36.7 MPLAB REAL ICE In-Circuit Emulator System 36.8 MPLAB ICD 3 In-Circuit Debugger System 36.9 PICkit 3 In-Circuit Debugger/ Programmer 36.10 MPLAB PM3 Device Programmer 36.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 36.12 Third-Party Development Tools 37.0 Packaging Information 37.1 Package Marking Information Package Marking Information (Continued) Package Marking Information (Continued) 37.2 Package Details Appendix A: Data Sheet Revision History Revision A (02/2014) Revision B (12/2015) Revision C (9/2018) The Microchip Website Customer Change Notification Service Customer Support Product Identification System ASIA/PACIFIC