Datasheet PIC16(L)F19155/56/75/76/85/86 (Microchip) - 5

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PIC16(L)F19155/56/75/76/85/86 FIGURE 2: 28-PIN UQFN PIN DIAGRAM FOR PIC16(L)F19155/56
14 G /SEG15 PP T /V /SEG13 /MCLR RA1/SEG1 RA0/SEG0 RE3 RB7/ICSPDA RB6/ICSPCLK/SE RB5/COM1 RB4/COM0 28 27 26 25 24 23 22 SEG2/RA2 1
P
21
IC1
RB3/CFLY2/COM6/SEG11 SEG3/RA3 2 20
6
RB2/CFLY1/COM7/SEG10 COM3/SEG2/RA4 3
(L)
19 RB1/SEG9
F19
VBAT/RA5 4 18 RB0/SEG8 V
1
SS 5
5
17 VDD
5
SEG7/RA7 6
/5
16 VSS
6
SEG6/RA6 7 15 RC7/VLCD1/COM4/SEG23 8 9 10 11 12 13 14 0 1 2 RC RC /RC VLCD3 G19/RC3 SE SEG20/RC4 COM2/SEG18 /SEG22/VLCD2/RC6 5 COM
Note 1:
See Table 3 for location of all peripheral functions.
2:
All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to float may result in degraded electrical performance or non-functionality.
3:
The bottom pad of the QFN/UQFN package should be connected to VSS at the circuit board level.  2017-2019 Microchip Technology Inc. DS40001923B-page 5 Document Outline Description Core Features Memory Operating Characteristics Power-Saving Functionality eXtreme Low-Power (XLP) Features Digital Peripherals Analog Peripherals Flexible Oscillator Structure FIGURE 1: 28-Pin SSOP, SPDIP and SOIC Pin Diagram for PIC16(L)F19155/56 FIGURE 2: 28-Pin UQFN Pin Diagram for PIC16(L)F19155/56 FIGURE 3: 40-Pin PDIP Pin Diagram for PIC16(L)F19175/76 FIGURE 4: 40-Pin UQFN (5x5x0,5) Pin Diagram for PIC16(L)F19175/76 FIGURE 5: 44-Pin TQFP Pin Diagram for PIC16(L)F19175/76 FIGURE 6: 48-Pin TQFP/UQFN Pin Diagram for PIC16(L)F19185/86 Pin Allocation Tables Table of Contents Most Current Data Sheet Errata Customer Notification System 1.0 Device Overview TABLE 1-1: Device Peripheral Summary EXAMPLE 1-1: Assembly Sequence 1 for Setting COG1 to Push-Pull Mode EXAMPLE 1-2: Assembly Sequence 2 for Setting COG1 to Push-Pull Mode FIGURE 1-1: PIC16(L)F19155/56/75/76/85/86 Block Diagram TABLE 1-2: PIC16(L)F19155/56 Pinout Description TABLE 1-3: PIC16(L)F19175/76 Pinout Description TABLE 1-4: PIC16(L)F19185/86 Pinout Description 2.0 Guidelines for Getting Started With PIC16(L)F19155/56/75/76/85/86 Microcontrollers FIGURE 2-1: Recommended Minimum Connections FIGURE 2-2: Suggested Placement of the Oscillator Circuit 3.0 Enhanced Mid-Range CPU FIGURE 3-1: Core Data Path Diagram 4.0 Memory Organization TABLE 4-1: Device Sizes and Addresses FIGURE 4-1: Program Memory Map and Stack for PIC16(L)F19155/56/75/76/85/86 EXAMPLE 4-1: RETLW Instruction EXAMPLE 4-2: Accessing Program Memory Via FSR TABLE 4-2: Memory Access Partition FIGURE 4-2: Banked Memory Partitioning TABLE 4-3: Core Registers Register 4-1: STATUS: STATUS Register TABLE 4-4: General Purpose RAM Size and Bank Location TABLE 4-5: General Purpose RAM Size and Bank Location TABLE 4-6: PIC16(L)F19155/56/75/76/85/86 Memory Map, Banks 0-7 TABLE 4-7: PIC16(L)F19155/56/75/76/85/86 Memory Map, Banks 8-15 TABLE 4-8: PIC16(L)F19155/56/75/76/85/86 Memory Map, Banks 16-23 TABLE 4-9: PIC16(L)F19155/56/75/76/85/86 Memory Map, Banks 24-29 TABLE 4-10: PIC16(L)F19155/56/75/76/85/86 Memory Map, Banks 58-63 TABLE 4-11: Special Function Register Summary Banks 0-63 (All Banks) TABLE 4-12: Special Function Register Summary Banks 0-63 PIC16(L)F19155/56/75/76/85/86 FIGURE 4-3: Loading Of PC In Different Situations FIGURE 4-4: Accessing the Stack Example 1 FIGURE 4-5: Accessing the Stack Example 2 FIGURE 4-6: Accessing the Stack Example 3 FIGURE 4-7: Accessing the Stack Example 4 FIGURE 4-8: Indirect Addressing PIC16(L)F19155/75/85 FIGURE 4-9: Indirect Addressing PIC16(L)F19156/76/86 FIGURE 4-10: Traditional/Banked Data Memory Map FIGURE 4-11: Linear Data Memory Map FIGURE 4-12: Program Flash Memory Map 5.0 Device Configuration Register 5-1: Configuration Word 1: Oscillators Register 5-2: Configuration Word 2: Supervisors Register 5-3: Configuration Word 3: Windowed Watchdog Register 5-4: Configuration Word 4: Memory TABLE 5-1: Boot Block Size Bits Register 5-5: Configuration Word 5: Code Protection Register 5-6: DevID: Device ID Register Register 5-7: RevisionID: Revision ID Register 6.0 Device Information Area TABLE 6-1: Device Information Area 7.0 Device Configuration Information TABLE 7-1: Device Configuration Information for PIC16(L)F19155/56/75/76/85/86 Family of Devices TABLE 7-2: Memory Size and Number of User Rows 8.0 Resets and Vbat FIGURE 8-1: Simplified Block Diagram of On-Chip Reset Circuit TABLE 8-1: BOR Operating Modes FIGURE 8-2: Brown-out Situations Register 8-1: BORCON: Brown-out Reset Control Register TABLE 8-2: MCLR Configuration FIGURE 8-3: Reset Start-up Sequence TABLE 8-3: Reset Status Bits and Their Significance TABLE 8-4: Reset Condition for Special Registers Register 8-2: PCON0: Power Control Register 0 Register 8-3: PCON1: Power Control Register 1 TABLE 8-5: Vdd Vs. Vbat TABLE 8-6: Summary of Registers Associated with Resets 9.0 Oscillator Module (with Fail-Safe Clock Monitor) FIGURE 9-1: Simplified PIC® MCU Clock Source Block Diagram FIGURE 9-2: External Clock (EC) Mode Operation FIGURE 9-3: Quartz Crystal Operation (Secondary Oscillator) FIGURE 9-4: Clock Switch (CSWHOLD = 0) FIGURE 9-5: Clock Switch (CSWHOLD = 1) FIGURE 9-6: Clock Switch Abandoned FIGURE 9-7: FSCM Block Diagram FIGURE 9-8: FSCM Timing Diagram Register 9-1: OSCCON1: Oscillator Control Register1 Register 9-2: OSCCON2: Oscillator Control Register 2(1) TABLE 9-1: NOSC/COSC Bit Settings TABLE 9-2: NDIV/CDIV Bit Settings Register 9-3: OSCCON3: Oscillator Control Register 3 Register 9-4: OSCSTAT: Oscillator STATUS Register 1 Register 9-5: OSCEN: Oscillator Manual Enable Register Register 9-6: OSCFRQ: HFINTOSC Frequency Selection Register Register 9-7: OSCTUNE: HFINTOSC Tuning Register Register 9-8: ACTCON: Active Clock Tuning (ACT) Control Register TABLE 9-3: Summary of Registers Associated with Clock Sources TABLE 9-4: Summary OF Configuration Word WITH Clock Sources 10.0 Interrupts FIGURE 10-1: Interrupt Logic FIGURE 10-2: Interrupt Latency FIGURE 10-3: INT Pin Interrupt Timing Register 10-1: INTCON: Interrupt Control Register Register 10-2: PIE0: Peripheral Interrupt Enable Register 0 Register 10-3: PIE1: Peripheral Interrupt Enable Register 1 Register 10-4: PIE2: Peripheral Interrupt Enable Register 2 Register 10-5: PIE3: Peripheral Interrupt Enable Register 3 Register 10-6: PIE4: Peripheral Interrupt Enable Register 4 Register 10-7: PIE5: Peripheral Interrupt Enable Register 5 Register 10-8: PIE6: Peripheral Interrupt Enable Register 6 Register 10-9: PIE7: Peripheral Interrupt Enable Register 7 Register 10-10: PIE8: Peripheral Interrupt Enable Register 8 Register 10-11: PIR0: Peripheral Interrupt Status Register 0 Register 10-12: PIR1: Peripheral Interrupt Request Register 1 Register 10-13: PIR2: Peripheral Interrupt Request Register 2 Register 10-14: PIR3: Peripheral Interrupt Request Register 3 Register 10-15: PIR4: Peripheral Interrupt Request Register 4 Register 10-16: PIR5: Peripheral Interrupt Request Register 5 Register 10-17: PIR6: Peripheral Interrupt Request Register 6 Register 10-18: PIR7: Peripheral Interrupt Request Register 7 Register 10-19: PIR8: Peripheral Interrupt Request Register 8 TABLE 10-1: Summary of Registers Associated with Interrupts 11.0 Power-Saving Operation Modes TABLE 11-1: System Behavior for Interrupt during Doze FIGURE 11-1: Doze Mode Operation Example FIGURE 11-2: Wake-Up From Sleep Through Interrupt Register 11-1: VREGCON: Voltage Regulator Control Register (1) Register 11-2: CPUDOZE: Doze and Idle Register TABLE 11-2: Summary of Registers Associated with Power-Down Mode 12.0 Windowed Watchdog Timer (WWDT) FIGURE 12-1: Watchdog Timer Block Diagram TABLE 12-1: WWDT Operating Modes TABLE 12-2: WWDT Clearing Conditions FIGURE 12-2: Window Period and Delay Register 12-1: WDTCON0: Watchdog Timer Control Register 0 Register 12-2: WDTCON1: Watchdog Timer Control Register 1 Register 12-3: WDTPSL: WDT Prescale Select Low Byte Register Register 12-4: WDTPSH: WDT Prescale Select High Byte Register Register 12-5: WDTTMR: WDT Timer Register TABLE 12-3: Summary of Registers Associated with Windowed Watchdog Timer TABLE 12-4: Summary OF Configuration Word WITH Watchdog Timer 13.0 Nonvolatile Memory (NVM) Control TABLE 13-1: Flash Memory Organization by Device FIGURE 13-1: Flash Program Memory Read Flowchart EXAMPLE 13-1: PFM Program Memory Read FIGURE 13-2: NVM Unlock Sequence Flowchart EXAMPLE 13-2: NVM Unlock Sequence FIGURE 13-3: NVM Erase Flowchart EXAMPLE 13-3: Erasing One Row of Program Flash Memory (PFM) TABLE 13-2: NVM Organization and Access Information FIGURE 13-4: Block Writes to Program Flash Memory (PFM) With 32 write latches FIGURE 13-5: Program Flash Memory (PFM) Write Flowchart EXAMPLE 13-4: Writing to Program Flash Memory (PFM) FIGURE 13-6: Flash Program Memory Modify Flowchart TABLE 13-3: NVRM Access to Device Information Area, Device Configuration Area, User ID, Device ID and Configuration Words (NVMREGS = 1) EXAMPLE 13-5: Device ID Access FIGURE 13-7: Flash Program Memory Verify Flowchart TABLE 13-4: Actions for PFM When WR = 1 Register 13-1: NVMDATL: Nonvolatile Memory Data Low Byte Register Register 13-2: NVMDATH: Nonvolatile Memory Data High Byte Register Register 13-3: NVMADRL: Nonvolatile Memory Address Low Byte Register Register 13-4: NVMADRH: Nonvolatile Memory Address High Byte Register Register 13-5: NVMCON1: Nonvolatile Memory Control 1 Register Register 13-6: NVMCON2: NONVOLATILE Memory Control 2 Register TABLE 13-5: Summary of Registers Associated with Nonvolatile Memory (NVM) 14.0 I/O Ports TABLE 14-1: Port Availability Per Device FIGURE 14-1: Generic I/O Port Operation EXAMPLE 14-1: Initializing PORTA Register 14-1: PORTA: PORTA Register Register 14-2: TRISA: PORTA Tri-State Register Register 14-3: LATA: PORTA Data Latch Register Register 14-4: ANSELA: PORTA Analog Select Register Register 14-5: WPUA: Weak Pull-Up PORTA Register Register 14-6: ODCONA: PORTA Open-Drain Control Register Register 14-7: SLRCONA: PORTA Slew Rate Control Register Register 14-8: INLVLA: PORTA Input Level Control Register TABLE 14-2: Summary of Registers Associated with PORTA EXAMPLE 14-2: Initializing PORTB Register 14-9: PORTB: PORTB Register Register 14-10: TRISB: PORTB Tri-State Register Register 14-11: LATB: PORTB Data Latch Register Register 14-12: ANSELB: PORTB Analog Select Register Register 14-13: WPUB: Weak Pull-Up PORTB Register Register 14-14: ODCONB: PORTB Open-Drain Control Register Register 14-15: SLRCONB: PORTB Slew Rate Control Register Register 14-16: INLVLB: PORTB Input Level Control Register Register 14-17: HIDRVB: PORTB High Drive Control Register TABLE 14-3: Summary of Registers Associated with PORTB Register 14-18: PORTC: PORTC Register Register 14-19: TRISC: PORTC Tri-State Register Register 14-20: LATC: PORTC Data Latch Register Register 14-21: WPUC: Weak Pull-Up PORTC Register Register 14-22: ODCONC: PORTC Open-Drain Control Register Register 14-23: SLRCONC: PORTC Slew Rate Control Register Register 14-24: INLVLC: PORTC Input Level Control Register TABLE 14-4: Summary of Registers Associated with PORTC EXAMPLE 14-3: Initializing PORTD Register 14-25: PORTD: PORTD Register(2) Register 14-26: TRISD: PORTD Tri-State Register(1) Register 14-27: LATD: PORTD Data Latch Register(2) Register 14-28: ANSELD: PORTD Analog Select Register(2) Register 14-29: WPUD: Weak Pull-Up PORTD Register(2) Register 14-30: ODCOND: PORTD Open-Drain Control Register(1) Register 14-31: SLRCOND: PORTD Slew Rate Control Register(1) Register 14-32: INLVLD: PORTD Input Level Control Register(1) TABLE 14-5: Summary of Registers Associated with PORTD(2) EXAMPLE 14-4: Initializing PORTE Register 14-33: PORTE: PORTE Register Register 14-34: TRISE: PORTE Tri-State Register Register 14-35: LATE: PORTE Data Latch Register(2) Register 14-36: ANSELE: PORTE Analog Select Register(2) Register 14-37: WPUE: Weak Pull-Up PORTE Register Register 14-38: ODCONE: PORTE Open-Drain Control Register(1) Register 14-39: SLRCONE: PORTe Slew Rate Control Register(1) Register 14-40: INLVLE: PORTE Input Level Control Register TABLE 14-6: Summary of Registers Associated with PORTE EXAMPLE 14-5: Initializing PORTF Register 14-41: PORTF: PORTF Register Register 14-42: TRISF: PORTF Tri-State Register Register 14-43: LATF: PORTF Data Latch Register Register 14-44: ANSELF: PORTF Analog Select Register Register 14-45: WPUF: Weak Pull-Up PORTF Register Register 14-46: ODCONF: PORTF Open-Drain Control Register Register 14-47: SLRCONF: PORTF Slew Rate Control Register Register 14-48: INLVLF: PORTF Input Level Control Register Register 14-49: HIDRVF: PORTF High Drive Control Register TABLE 14-7: Summary of Registers Associated with PORTF(1) 15.0 Peripheral Pin Select (PPS) Module FIGURE 15-1: Simplified PPS Block Diagram TABLE 15-1: PPS Input Signal Routing Options TABLE 15-2: PPS Input Register Values EXAMPLE 15-1: PPS Lock/Unlock sequence TABLE 15-3: PPS Output Signal Routing Options Register 15-1: XXXPPS: Peripheral xxx input Selection(1) Register 15-2: RxyPPS: Pin Rxy Output Source Selection Register Register 15-3: PPSLOCK: PPS Lock Register TABLE 15-4: Summary of Registers Associated with the PPS Module 16.0 Peripheral Module Disable (PMD) Register 16-1: PMD0: PMD Control Register 0 Register 16-2: PMD1: PMD Control Register 1 Register 16-3: PMD2: PMD Control Register 2 Register 16-4: PMD3: PMD Control Register 3 Register 16-5: PMD4: PMD Control Register 4 Register 16-6: PMD5 – PMD Control Register 5 17.0 Interrupt-On-Change (IOC) EXAMPLE 17-1: Clearing Interrupt Flags (PORTB Example) FIGURE 17-1: Interrupt-On-Change Block Diagram (PORTB Example) Register 17-1: IOCAP: Interrupt-on-Change PORTA Positive Edge Register Register 17-2: IOCAN: Interrupt-on-Change PORTA Negative Edge Register Register 17-3: IOCAF: Interrupt-on-Change PORTA Flag Register Register 17-4: IOCBP: Interrupt-on-Change PORTB Positive Edge Register Register 17-5: IOCBN: Interrupt-on-Change PORTB Negative Edge Register Register 17-6: IOCBF: Interrupt-on-Change PORTB Flag Register Register 17-7: IOCCP: Interrupt-on-Change PORTC Positive Edge Register Register 17-8: IOCCN: Interrupt-on-Change PORTC Negative Edge Register Register 17-9: IOCCF: Interrupt-on-Change PORTC Flag Register Register 17-10: IOCEP: Interrupt-on-Change PORTE Positive Edge Register Register 17-11: IOCEN: Interrupt-on-Change PORTE Negative Edge Register Register 17-12: IOCEF: Interrupt-on-Change PORTE Flag Register TABLE 17-1: Summary of Registers Associated with Interrupt-On-Change 18.0 Fixed Voltage Reference (FVR) FIGURE 18-1: Voltage Reference Block Diagram Register 18-1: FVRCON: Fixed Voltage Reference Control Register TABLE 18-1: Summary of Registers Associated with Fixed Voltage Reference 19.0 Analog-to-Digital Converter with Computation (ADC2) Module FIGURE 19-1: ADC2 Block Diagram TABLE 19-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies(1,4) FIGURE 19-2: Analog-to-Digital Conversion Tad Cycles FIGURE 19-3: 12-Bit ADC Conversion Result Format EQUATION 19-1: Acquisition Time Example FIGURE 19-4: Analog Input Model FIGURE 19-5: ADC Transfer Function FIGURE 19-6: Hardware Capacitive Voltage Divider Block Diagram FIGURE 19-7: Differential CVD Measurement Waveform FIGURE 19-8: Guard Ring Circuit FIGURE 19-9: Differential CVD with Guard Ring Output Waveform FIGURE 19-10: Computational Features Simplified Block Diagram TABLE 19-2: Computation Modes TABLE 19-3: Low-pass Filter -3 dB Cut-off Frequency Register 19-1: ADCON0: ADC Control Register 0 Register 19-2: ADCON1: ADC Control Register 1 Register 19-3: ADCON2: ADC Control Register 2 Register 19-4: ADCON3: ADC Control Register 3 Register 19-5: ADSTAT: ADC Status Register Register 19-6: ADCLK: ADC Clock Selection Register Register 19-7: ADREF: ADC Reference Selection Register Register 19-8: ADPCH: ADC Positive Channel Selection Register Register 19-9: ADPREL: ADC Precharge Time Control Register (Low Byte) Register 19-10: ADPREH: ADC Precharge Time Control Register (High Byte) TABLE 19-4: Precharge Time Register 19-11: ADACQL: ADC Acquisition Time Control Register (Low Byte) Register 19-12: ADACQH: ADC Acquisition Time Control Register (High Byte) TABLE 19-5: Acquisition Time Register 19-13: ADCAP: ADC Additional Sample Capacitor Selection Register Register 19-14: ADRPT: ADC Repeat Setting Register Register 19-15: ADCNT: ADC Repeat Counter Register Register 19-16: ADFLTRH: ADC Filter High Byte Register Register 19-17: ADFLTRL: ADC Filter Low Byte Register Register 19-18: ADRESH: ADC Result Register High, FM = 0 Register 19-19: ADRESL: ADC Result Register Low, FM = 0 Register 19-20: ADRESH: ADC Result Register High, FM = 1 Register 19-21: ADRESL: ADC Result Register Low, FM = 1 Register 19-22: ADPREVH: ADC Previous Result Register Register 19-23: ADPREVL: ADC Previous Result Register Register 19-24: ADACCU: ADC Accumulator Register Upper Register 19-25: ADACCH: ADC Accumulator Register High Register 19-26: ADACCL: ADC Accumulator Register Low Register 19-27: ADSTPTH: ADC Threshold Setpoint Register High Register 19-28: ADSTPTL: ADC Threshold Setpoint Register Low Register 19-29: ADERRH: ADC Setpoint Error Register High Register 19-30: ADERRL: ADC Setpoint Error Low Byte Register Register 19-31: ADLTHH: ADC Lower Threshold High Byte Register Register 19-32: ADLTHL: ADC Lower Threshold Low Byte Register Register 19-33: ADUTHH: ADC Upper Threshold High Byte Register Register 19-34: ADUTHL: ADC Upper Threshold Low Byte Register Register 19-35: ADACT: ADC AUTO-Conversion Trigger Control Register Register 19-36: ADCPCON0: ADC Charge Pump Control Register TABLE 19-6: Summary of Registers Associated with ADC 20.0 Temperature Indicator Module (TIM) FIGURE 20-1: Temperature Circuit Diagram EQUATION 20-1: Sensor Temperature EQUATION 20-2: Temperature Resolution (°C/LSb) TABLE 20-1: Recommended Vdd vs. Range TABLE 20-2: Summary of Registers Associated with the Temperature Indicator 21.0 5-Bit Digital-to-Analog Converter (DAC1) Module EQUATION 21-1: DAC Output Voltage FIGURE 21-1: Digital-to-Analog Converter Block Diagram FIGURE 21-2: Voltage Reference Output Buffer Example Register 21-1: DAC1CON0: Voltage Reference Control Register 0 Register 21-2: DAC1CON1: Voltage Reference Control Register 1 TABLE 21-1: Summary of Registers Associated with the DAC1 Module 22.0 Comparator Module TABLE 22-1: Available Comparators FIGURE 22-1: Single Comparator FIGURE 22-2: Comparator Module Simplified Block Diagram TABLE 22-2: Comparator Output State vs. Input Conditions FIGURE 22-3: Analog Input Model Register 22-1: CMxCON0: Comparator Cx Control Register 0 Register 22-2: CMxCON1: Comparator Cx Control Register 1 Register 22-3: CMxNSEL: Comparator Cx Negative Input Select Register Register 22-4: CMxPSEL: Comparator Cx Positive Input Select Register Register 22-5: CMOUT: Comparator Output Register TABLE 22-3: Summary of Registers Associated with Comparator Module 23.0 Zero-Cross Detection (ZCD) Module EQUATION 23-1: External Resistor FIGURE 23-1: External Voltage FIGURE 23-2: Simplified ZCD Block Diagram EQUATION 23-2: R-C Calculations EXAMPLE 23-1: R-C Calculations Example EQUATION 23-3: ZCD Event Offset EQUATION 23-4: ZCD Pull-up/down EQUATION 23-5: Series R for V range Register 23-1: ZCDCON: Zero-Cross Detection Control Register TABLE 23-1: Summary of Registers Associated with the ZCD Module TABLE 23-2: Summary of Configuration Word with the ZCD Module 24.0 Real-Time Clock and Calendar (RTCC) FIGURE 24-1: RTCC Block Diagram Control Registers Clock Value Registers Alarm Value Registers FIGURE 24-2: Binary Coded Decimal (BCD) Timer Digit Format FIGURE 24-3: Binary Coded Decimal (BCD) Alarm Digit Format FIGURE 24-4: Clock Source Multiplexing TABLE 24-1: Day of Week Schedule TABLE 24-2: Day to Month Rollover Schedule EQUATION 24-1: Converting Error Clock Pulses FIGURE 24-5: Alarm Mask Settings Register 24-1: RTCCON: RTC Control Register Register 24-2: RTCCAL: RTC Calibration Register Register 24-3: Year(1): Year Value Register Register 24-4: Month(1): Month Value Register Register 24-5: Weekday(1): Weekday Value Register Register 24-6: Day(1): Day Value Register Register 24-7: Hours(1): Hour Value Register Register 24-8: Minutes(1): Minute Value Register Register 24-9: Seconds(1): Second Value Register Register 24-10: ALRMCON: Alarm Control Register Register 24-11: ALRMRPT: Alarm Repeat Register Register 24-12: ALRMMTH: Alarm Month Control Register Register 24-13: ALRMWd: Alarm Weekday Control Register Register 24-14: ALRMDAY: Alarm Day Control Register Register 24-15: ALRMHr: Alarm Hour Control Register Register 24-16: ALRMMIN: Alarm Minute Control Register Register 24-17: ALRMSEC: Alarm Seconds Control Register TABLE 24-3: Summary of Registers associated with the RTCC Module 25.0 Timer0 Module FIGURE 25-1: Block Diagram of Timer0 Register 25-1: T0CON0: TIMER0 Control Register 0 Register 25-2: T0CON1: TIMER0 Control Register 1 TABLE 25-1: Summary of Registers Associated with Timer0 26.0 Timer1 Module with Gate Control FIGURE 26-1: Timer1 Block Diagram TABLE 26-1: Timer1 Enable Selections TABLE 26-2: Timer Gate Enable Selections FIGURE 26-2: Timer1 Incrementing Edge FIGURE 26-3: Timer1 Gate Enable Mode FIGURE 26-4: Timer1 Gate Toggle Mode FIGURE 26-5: Timer1 Gate Single-Pulse Mode FIGURE 26-6: Timer1 Gate Single-Pulse and Toggle Combined Mode Register 26-1: T1CON: Timer1 Control Register Register 26-2: T1GCON: Timer1 Gate Control Register Register 26-3: T1CLK Timer1 Clock Select Register Register 26-4: T1GATE Timer1 Gate Select Register TABLE 26-3: Summary of Registers Associated with Timer1 27.0 Timer2/4 Module With Hardware Limit Timer (HLT) FIGURE 27-1: Timer2/4 Block Diagram FIGURE 27-2: Timer2/4 Clock Source Block Diagram TABLE 27-1: Timer2/4 Operating Modes FIGURE 27-3: Timer2 Prescaler, Postscaler, and Interrupt Timing Diagram FIGURE 27-4: Software Gate Mode Timing Diagram (MODE = 00000) FIGURE 27-5: Hardware Gate Mode Timing Diagram (MODE = 00001) FIGURE 27-6: Edge-Triggered Hardware Limit Mode Timing Diagram (MODE = 00100) FIGURE 27-7: Level-Triggered Hardware Limit Mode Timing Diagram (MODE = 00111) FIGURE 27-8: Software Start One-shot Mode Timing Diagram (MODE = 01000) FIGURE 27-9: Edge-Triggered One-Shot Mode Timing Diagram (MODE = 01001) FIGURE 27-10: Edge-Triggered Hardware Limit One-Shot Mode Timing Diagram (MODE = 01100) FIGURE 27-11: Low Level Reset, Edge-Triggered hardware Limit one-Shot Mode Timing Diagram (MODE = 01110) FIGURE 27-12: Rising Edge-Triggered Monostable Mode Timing Diagram (MODE = 10001) FIGURE 27-13: Level-Triggered hardware Limit one-Shot Mode Timing Diagram (MODE = 10110) Register 27-1: TXCLKCON: Timer2/4 Clock Selection Register Register 27-2: TxCON: Timer2/4 Control Register Register 27-3: TxHLT: Timer2/4 Hardware Limit Control Register Register 27-4: TxRST: Timer2/4 External Reset Signal Selection Register TABLE 27-2: Summary of Registers Associated with Timer2/4 28.0 Signal Measurement Timer (SMT) FIGURE 28-1: SMTx Block Diagram FIGURE 28-2: SMTx Signal and Window Block Diagram TABLE 28-1: Register 28-1: SMTxCON0: SMT Control Register 0 Register 28-2: SMTxCON1: SMT Control Register 1 Register 28-3: SMTxSTAT: SMT Status Register Register 28-4: SMTxCLK: SMT Clock Selection Register Register 28-5: SMTxWIN: SMTx Window Input Select Register Register 28-6: SMTxSIG: SMTx Signal Input Select Register Register 28-7: SMTxTMRL: SMT Timer Register – Low Byte Register 28-8: SMTxTMRH: SMT Timer Register – High Byte Register 28-9: SMTxTMRU: SMT Timer Register – Upper Byte Register 28-10: SMTxCPRL: SMT Captured Period Register – Low Byte Register 28-11: SMTxCPRH: SMT Captured Period Register – High Byte Register 28-12: SMTxCPRU: SMT Captured Period Register – Upper Byte Register 28-13: SMTxCPWL: SMT Captured Pulse Width Register – Low Byte Register 28-14: SMTxCPWH: SMT Captured Pulse Width Register – High Byte Register 28-15: SMTxCPWU: SMT Captured Pulse Width Register – Upper Byte Register 28-16: SMTxPRL: SMT Period Register – Low Byte Register 28-17: SMTxPRH: SMT Period Register – High Byte Register 28-18: SMTxPRU: SMT Period Register – Upper Byte TABLE 28-2: Modes of Operation FIGURE 28-3: Timer Mode Timing Diagram FIGURE 28-4: Gated Timer Mode Repeat Acquisition Timing Diagram FIGURE 28-5: Gated Timer Mode Single Acquisition Timing Diagram FIGURE 28-6: Period And Duty-Cycle Repeat Acquisition Mode Timing Diagram FIGURE 28-7: Period And Duty-Cycle Single Acquisition Timing Diagram FIGURE 28-8: High and Low-Measure Mode Repeat Acquisition Timing Diagram FIGURE 28-9: High and Low-Measure Mode Single Acquisition Timing Diagram FIGURE 28-10: Windowed Measure Mode Repeat Acquisition Timing Diagram FIGURE 28-11: Windowed Measure Mode Single Acquisition Timing Diagram FIGURE 28-12: Gated Windowed Measure Mode Repeat Acquisition Timing Diagram FIGURE 28-13: Gated Windowed Measure Mode Single Acquisition Timing Diagrams FIGURE 28-14: Time Of Flight Mode Repeat Acquisition Timing Diagram FIGURE 28-15: Time Of Flight Mode Single Acquisition Timing Diagram FIGURE 28-16: Capture Mode Repeat Acquisition Timing Diagram FIGURE 28-17: Capture Mode Single Acquisition Timing Diagram FIGURE 28-18: Counter Mode Timing Diagram FIGURE 28-19: Gated Counter Mode Repeat Acquisition Timing Diagram FIGURE 28-20: Gated Counter Mode Single Acquisition Timing Diagram FIGURE 28-21: Windowed Counter Mode Repeat Acquisition Timing Diagram FIGURE 28-22: Windowed Counter Mode Single Acquisition Timing Diagram TABLE 28-3: Summary of Registers Associated with SMTx 29.0 Capture/Compare/PWM Modules TABLE 29-1: Available CCP Modules FIGURE 29-1: Capture Mode Operation Block Diagram EXAMPLE 29-1: Changing Between Capture Prescalers FIGURE 29-2: Compare Mode Operation Block Diagram FIGURE 29-3: CCP PWM Output Signal FIGURE 29-4: Simplified PWM Block Diagram EQUATION 29-1: PWM Period FIGURE 29-5: PWM 10-Bit Alignment EQUATION 29-2: Pulse Width EQUATION 29-3: Duty Cycle Ratio EQUATION 29-4: PWM Resolution TABLE 29-2: Example PWM Frequencies and Resolutions (Fosc = 20 MHz) TABLE 29-3: Example PWM Frequencies and Resolutions (Fosc = 8 MHz) TABLE 29-4: Long Bit Names Prefixes for CCP Peripherals Register 29-1: CCPxCON: CCPx Control Register Register 29-2: CCPxCAP: Capture Input Selection Register Register 29-3: CCPRxL Register: CCPx Register Low Byte Register 29-4: CCPRxH Register: CCPx Register High Byte Register 29-5: CCPTMRS0: CCP Timers Control 0 Register TABLE 29-5: Summary Of Registers Associated with CCPx 30.0 Pulse-Width Modulation (PWM) FIGURE 30-1: PWM Output FIGURE 30-2: Simplified PWM Block Diagram EQUATION 30-1: PWM Period EQUATION 30-2: Pulse Width EQUATION 30-3: Duty Cycle Ratio EQUATION 30-4: PWM Resolution TABLE 30-1: Example PWM Frequencies and Resolutions (Fosc = 20 MHz) TABLE 30-2: Example PWM Frequencies and Resolutions (Fosc = 8 MHz) Register 30-1: PWMxCON: PWM Control Register Register 30-2: PWMXDCH: PWM Duty Cycle High Bits Register 30-3: PWMxDCL: PWM Duty Cycle Low Bits TABLE 30-3: Summary of Registers Associated with PWMx 31.0 Complementary Waveform Generator (CWG) Module TABLE 31-1: Available CWG Modules FIGURE 31-1: Simplified CWG Block Diagram (Half-Bridge Mode) FIGURE 31-2: Simplified CWG Block Diagram (Push-Pull Mode) FIGURE 31-3: Simplified CWG Block Diagram (Forward and Reverse Full-Bridge Modes) FIGURE 31-4: Simplified CWG Block Diagram (Output Steering Modes) FIGURE 31-5: CWG Output Block Diagram FIGURE 31-6: Dead-Band Operation CWG1DBR = 0x01, CWG1DBF = 0x02 FIGURE 31-7: Dead-Band Operation, CWG1DBR = 0x03, CWG1DBF = 0x04, Source Shorter Than Dead Band EQUATION 31-1: Dead-Band Uncertainty FIGURE 31-8: Example of PWM Direction Change FIGURE 31-9: CWG Half-Bridge Mode Operation FIGURE 31-10: Example of Asynchronous Steering Event (MODE<2:0> = 000) FIGURE 31-11: Example of Steering Event (MODE<2:0> = 001) FIGURE 31-12: CWG Shutdown Block Diagram FIGURE 31-13: Shutdown Functionality, Auto-Restart Disabled (REN = 0, LSAC = 01, LSBD = 01) FIGURE 31-14: Shutdown Functionality, Auto-Restart Enabled (REN = 1, LSAC = 01, LSBD = 01) Register 31-1: CWG1CON0: CWG1 Control Register 0 Register 31-2: CWG1CON1: CWG1 Control Register 1 Register 31-3: CWG1DBR: CWG1 Rising Dead-Band Counter Register Register 31-4: CWG1DBF: CWG1 Falling Dead-Band Counter Register Register 31-5: CWG1AS0: CWG1 Auto-Shutdown Control Register 0 Register 31-6: CWG1AS1: CWG1 Auto-Shutdown Control Register 1 Register 31-7: CWG1STR: CWG1 Steering Control Register(1) Register 31-8: CWG1CLK: CWG1 Clock Selection Register Register 31-9: CWG1ISM: CWG1 Input Selection Register TABLE 31-2: Summary of Registers Associated with CWG 32.0 Configurable Logic Cell (CLC) TABLE 32-1: Available CLC Modules FIGURE 32-1: CLCx Simplified Block Diagram TABLE 32-2: CLCx Data Input Selection TABLE 32-3: Data Gating Logic Examples FIGURE 32-2: Input Data Selection and Gating FIGURE 32-3: Programmable Logic Functions Register 32-1: CLCxCON: Configurable Logic Cell Control Register Register 32-2: CLCxPOL: Signal Polarity Control Register Register 32-3: CLCxSEL0: Generic CLCx Data 0 Select Register Register 32-4: CLCxSEL1: Generic CLCx Data 1 Select Register Register 32-5: CLCxSEL2: Generic CLCx Data 2 Select Register Register 32-6: CLCxSEL3: Generic CLCx Data 3 Select Register Register 32-7: CLCxGLS0: Gate 0 Logic Select Register Register 32-8: CLCxGLS1: Gate 1 Logic Select Register Register 32-9: CLCxGLS2: Gate 2 Logic Select Register Register 32-10: CLCxGLS3: Gate 3 Logic Select Register Register 32-11: CLCDATA: CLC Data Output TABLE 32-4: Summary of Registers Associated with CLCx 33.0 Master Synchronous Serial Port (MSSP) Modules FIGURE 33-1: MSSP Block Diagram (SPI mode) FIGURE 33-2: MSSP Block Diagram (I2C Master mode) FIGURE 33-3: MSSP Block Diagram (I2C Slave mode) FIGURE 33-4: SPI Master and Multiple Slave Connection FIGURE 33-5: SPI Master/Slave Connection FIGURE 33-6: SPI Mode Waveform (Master Mode) FIGURE 33-7: SPI Daisy-Chain Connection FIGURE 33-8: Slave Select Synchronous Waveform FIGURE 33-9: SPI Mode Waveform (Slave Mode with CKE = 0) FIGURE 33-10: SPI Mode Waveform (Slave Mode with CKE = 1) FIGURE 33-11: I2C Master/ Slave Connection TABLE 33-1: I2C Bus terms FIGURE 33-12: I2C Start and Stop Conditions FIGURE 33-13: I2C Restart Condition FIGURE 33-14: I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0) FIGURE 33-15: I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 33-16: I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1) FIGURE 33-17: I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1) FIGURE 33-18: I2C Slave, 7-bit Address, Transmission (AHEN = 0) FIGURE 33-19: I2C Slave, 7-bit Address, Transmission (AHEN = 1) FIGURE 33-20: I2C Slave, 10-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 33-21: I2C Slave, 10-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 0) FIGURE 33-22: I2C Slave, 10-bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0) FIGURE 33-23: Clock Synchronization Timing FIGURE 33-24: Slave Mode General Call Address Sequence FIGURE 33-25: Baud Rate Generator Timing with Clock Arbitration FIGURE 33-26: First Start Bit Timing FIGURE 33-27: Repeated Start Condition Waveform FIGURE 33-28: I2C Master Mode Waveform (Transmission, 7 or 10-bit Address) FIGURE 33-29: I2C Master Mode Waveform (Reception, 7-bit Address) FIGURE 33-30: Acknowledge Sequence Waveform FIGURE 33-31: Stop Condition Receive or Transmit Mode FIGURE 33-32: Bus Collision Timing for Transmit and Acknowledge FIGURE 33-33: Bus Collision During Start Condition (SDA Only) FIGURE 33-34: Bus Collision During Start Condition (SCL = 0) FIGURE 33-35: BRG Reset Due to SDA Arbitration During Start Condition FIGURE 33-36: Bus Collision During a Repeated Start Condition (Case 1) FIGURE 33-37: Bus Collision During Repeated Start Condition (Case 2) FIGURE 33-38: Bus Collision During a Stop Condition (Case 1) FIGURE 33-39: Bus Collision During a Stop Condition (Case 2) FIGURE 33-40: Baud Rate Generator Block Diagram TABLE 33-2: MSSP Clock Rate w/BRG Register 33-1: SSPxSTAT: SSPx STATUS Register Register 33-2: SSPxCON1: SSPx Control Register 1 Register 33-3: SSPxCON2: SSPx Control Register 2 (I2C Mode Only)(1) Register 33-4: SSPxCON3: SSPx Control Register 3 Register 33-5: SSPxMSK: SSPx Mask Register Register 33-6: SSPxADD: MSSPx Address and Baud Rate Register (I2C Mode) Register 33-7: SSPxBUF: MSSPx Buffer Register TABLE 33-3: Summary of Registers Associated with MSSPX 34.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART1/2) FIGURE 34-1: EUSART Transmit Block Diagram FIGURE 34-2: EUSART Receive Block Diagram FIGURE 34-3: Asynchronous Transmission FIGURE 34-4: Asynchronous Transmission (Back-to-Back) FIGURE 34-5: Asynchronous Reception EXAMPLE 34-1: Calculating Baud Rate Error TABLE 34-1: BRG Counter Clock Rates FIGURE 34-6: Automatic Baud Rate Calibration FIGURE 34-7: Auto-Wake-up Bit (WUE) Timing During Normal Operation FIGURE 34-8: Auto-Wake-up Bit (WUE) Timings During Sleep FIGURE 34-9: Send Break Character Sequence FIGURE 34-10: Synchronous Transmission FIGURE 34-11: Synchronous Transmission (Through TXEN) FIGURE 34-12: Synchronous Reception (Master Mode, SREN) Register 34-1: TXxSTA: Transmit Status and Control Register Register 34-2: RCxSTA: Receive Status and Control Register Register 34-3: BAUDxCON: Baud Rate Control Register Register 34-4: RCxREG(1): Receive Data Register Register 34-5: TXxREG(1): Transmit Data Register Register 34-6: SPxBRGL(1): Baud Rate Generator Register Register 34-7: SPxBRGH(1, 2): Baud Rate Generator High Register TABLE 34-2: Summary of Registers Associated with EUSART TABLE 34-3: Baud Rate Formulas TABLE 34-4: Baud Rate For Asynchronous Modes 35.0 Liquid Crystal Display (LCD) Controller TABLE 35-1: Multiplexing Options FIGURE 35-1: LCD Controller Module Block Diagram TABLE 35-2: LCDSEx REGISTERS AND ASSOCIATED SEGMENTS TABLE 35-3: LCDDATAx Registers and Bits for Segment and COM Combinations (28-Pin) TABLE 35-4: LCDDATAx Registers and Bits for Segment and COM Combinations (40/44-Pin) TABLE 35-5: LCDDATAx Registers and Bits for Segment and COM Combinations (48-Pin) FIGURE 35-2: LCD Clock Generation TABLE 35-6: Internal Resistance Ladder Power Modes FIGURE 35-3: LCD Reference Ladder Power Mode Switching Diagram FIGURE 35-4: Internal Reference And Contrast Control Block Diagram TABLE 35-7: LCD Modes with Internal Charge Pump FIGURE 35-5: LCD Regulator Connections For LCD Voltage Supplied from Charge Pump with and without Internal Resistor Ladder FIGURE 35-6: Connections For LCD Voltage Supplied from External Ladder, Static, 1/2 and 1/3 Bias Modes (LCDVSRC<3:0> = 1000) FIGURE 35-7: Connections for LCD Voltage Supplied Externally or from Vdd along with Internal Resistor Ladder and External Capacitors, Static, 1/2 and 1/3 Bias Modes (LCDVSRC<3:0> = 0100, 0101) TABLE 35-8: COM<7:0> Pin Functions TABLE 35-9: Frame Frequency Formulas FIGURE 35-8: Type-A/Type-B Waveforms In Static Drive FIGURE 35-9: Type-A Waveforms In 1/2 Mux, 1/2 Bias Drive FIGURE 35-10: Type-B Waveforms In 1/2 Mux, 1/2 Bias Drive FIGURE 35-11: Type-A Waveforms In 1/3 Mux, 1/3 Bias Drive FIGURE 35-12: Type-B Waveforms In 1/3 Mux, 1/3 Bias Drive FIGURE 35-13: Type-A Waveforms In 1/4 Mux, 1/3 Bias Drive FIGURE 35-14: Type-B Waveforms In 1/4 Mux, 1/3 Bias Drive FIGURE 35-15: Type-B Waveforms In 1/8 Mux, 1/3 Bias Drive FIGURE 35-16: Example Waveforms And Interrupt Timing In Quarter Duty Cycle Drive FIGURE 35-17: Sleep Entry/Exit When SLPEN = 1 or CS<1:0> = 00 Register 35-1: LCDCON: LCD Control Register Register 35-2: LCDPS: LCD Phase Register Register 35-3: LCDSEx: LCD SEGMENT x Enable Register Register 35-4: LCDDATAx: LCD DATA x Register Register 35-5: LCDVCON1: LCD Voltage Control 1 Bits Register 35-6: LCDVCON2: LCD Voltage Control 2 Bits Register 35-7: LCDRL: LCD Internal Reference Ladder Control Register Register 35-8: LCDREF: LCD Reference Voltage/Contrast Control Register TABLE 35-10: Summary of Registers Associated with LCD Module 36.0 In-Circuit Serial Programming™ (ICSP™) FIGURE 36-1: ICD RJ-11 Style Connector Interface FIGURE 36-2: PICkit™ Programmer Style Connector Interface FIGURE 36-3: Typical Connection for ICSP™ Programming 37.0 Instruction Set Summary TABLE 37-1: Opcode Field Descriptions TABLE 37-2: Abbreviation Descriptions TABLE 37-3: Instruction Set TABLE 37-3: PIC16(L)F19155/56/75/76/85/86 Instruction Set (Continued) 38.0 Register Summary TABLE 38-1: Register File Summary for PIC16(L)F19155/56/75/76/85/86 Devices 39.0 Electrical Specifications FIGURE 39-1: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC16F19155/56/75/76/85/86 Only FIGURE 39-2: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC16(L)F19155/56/75/76/85/86 Only TABLE 39-1: Supply Voltage FIGURE 39-3: POR and POR Rearm with Slow Rising Vdd TABLE 39-2: Supply Current (Idd/Ibat)(1,2,4) TABLE 39-3: Power-Down Current (Ipd)(1,2) TABLE 39-4: I/O Ports TABLE 39-5: Memory Programming Specifications TABLE 39-6: Thermal characteristics FIGURE 39-4: Load Conditions FIGURE 39-5: Clock Timing TABLE 39-7: External Clock/Oscillator Timing Requirements TABLE 39-8: iNTERNAL Oscillator Parameters(1) FIGURE 39-6: Precision Calibrated HFINTOSC Frequency Accuracy Over Device Vdd and Temperature TABLE 39-9: PLL Specifications FIGURE 39-7: CLKOUT and I/O Timing TABLE 39-10: I/O and CLKOUT Timing Specifications FIGURE 39-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing FIGURE 39-9: Brown-out Reset Timing and Characteristics TABLE 39-11: Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-out Reset and Low-Power Brown-out Reset Specifications TABLE 39-12: Analog-to-Digital Converter (ADC) Accuracy Specifications(1,2) TABLE 39-13: Analog-to-Digital Converter (ADC) Conversion Timing Specifications FIGURE 39-10: ADC Conversion Timing (ADC Clock Fosc-based) FIGURE 39-11: ADC Conversion Timing (ADC Clock from ADCRC) TABLE 39-14: Comparator Specifications TABLE 39-15: Low-Powered Clocked Comparator Specifications TABLE 39-16: 5-Bit DAC Specifications TABLE 39-17: Fixed Voltage Reference (FVR) Specifications TABLE 39-18: Zero-Cross Detect (ZCD) Specifications FIGURE 39-12: Timer0 and Timer1 External Clock Timings TABLE 39-19: Timer0 and Timer1 External Clock Requirements FIGURE 39-13: Capture/Compare/PWM Timings (CCP) TABLE 39-20: Capture/Compare/PWM Requirements (CCP) FIGURE 39-14: CLC Propagation Timing TABLE 39-21: Configurable Logic Cell (CLC) Characteristics FIGURE 39-15: EUSART Synchronous Transmission (Master/Slave) Timing TABLE 39-22: EUSART Synchronous Transmission Characteristics FIGURE 39-16: EUSART Synchronous Receive (Master/Slave) Timing TABLE 39-23: EUSART Synchronous Receive Requirements FIGURE 39-17: SPI Master Mode Timing (CKE = 0, SMP = 0) FIGURE 39-18: SPI Master Mode Timing (CKE = 1, SMP = 1) FIGURE 39-19: SPI Slave Mode Timing (CKE = 0) FIGURE 39-20: SPI Slave Mode Timing (CKE = 1) TABLE 39-24: SPI Mode requirements FIGURE 39-21: I2C Bus Start/Stop Bits Timing TABLE 39-25: I2C Bus Start/Stop Bits Requirements FIGURE 39-22: I2C Bus Data Timing TABLE 39-26: I2C Bus Data Requirements 40.0 DC and AC Characteristics Graphs and Charts 41.0 Development Support 42.0 Packaging Information Appendix A: Data Sheet Revision History Revision B (6/2019) Revision A (6/2017) The Microchip WebSite Customer Change Notification Service Customer Support Product Identification System Trademarks Worldwide Sales