Datasheet PIC16(L)F18424/44 (Microchip) - 7
| Manufacturer | Microchip |
| Description | 14/20-Pin Full-Featured, Low Pin Count Microcontrollers with XLP |
| Pages / Page | 707 / 7 — PIC16(L)F18424/44. 20-Pin Diagrams. Figure 3. 20-Pin PDIP, SOIC, SSOP. … |
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| Document Language | English |
PIC16(L)F18424/44. 20-Pin Diagrams. Figure 3. 20-Pin PDIP, SOIC, SSOP. Figure 4. 20-Pin UQFN (4x4). Note: . Datasheet
Model Line for this Datasheet
- PIC16F18424-E/JQ PIC16F18424-E/P PIC16F18424-E/SL PIC16F18424-E/ST PIC16F18424-E/STVAO PIC16F18424-I/JQ PIC16F18424-I/P PIC16F18424-I/SL PIC16F18424-I/ST PIC16F18424T-E/SL PIC16F18424T-E/STVAO PIC16F18424T-I/JQ PIC16F18424T-I/SL PIC16F18424T-I/ST PIC16LF18424-E/JQ PIC16LF18424-E/P PIC16LF18424-E/SL PIC16LF18424-E/ST PIC16LF18424-I/JQ PIC16LF18424-I/P PIC16LF18424-I/SL PIC16LF18424-I/ST PIC16LF18424T-I/JQ PIC16LF18424T-I/SL PIC16LF18424T-I/ST
- PIC16F18444-E/GZ PIC16F18444-E/P PIC16F18444-E/SO PIC16F18444-E/SS PIC16F18444-I/GZ PIC16F18444-I/P PIC16F18444-I/SO PIC16F18444-I/SS PIC16F18444T-I/GZ PIC16F18444T-I/SO PIC16F18444T-I/SS PIC16LF18444-E/GZ PIC16LF18444-E/P PIC16LF18444-E/SO PIC16LF18444-E/SS PIC16LF18444-I/GZ PIC16LF18444-I/P PIC16LF18444-I/SO PIC16LF18444-I/SS PIC16LF18444T-I/GZ PIC16LF18444T-I/SO PIC16LF18444T-I/SS
Text Version of Document
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PIC16(L)F18424/44 20-Pin Diagrams Figure 3. 20-Pin PDIP, SOIC, SSOP
Rev. 00-000020A 6/21/2017 VDD 1 20 VSS RA5 2 19 RA0/ICSPDAT RA4 3 18 RA1/ICSPCLK MCLR/VPP/RA3 4 17 RA2 RC5 5 16 RC0 RC4 6 15 RC1 RC3 7 14 RC2 RC6 8 13 RB4 RC7 9 12 RB5 RB7 10 11 RB6
Figure 4. 20-Pin UQFN (4x4)
Rev. 00-000020B 6/21/2016 T DA P ICS 4 5 D S 0/ D S RA RA V V RA 20 19 18 17 16 MCLR/VPP/RA3 1 15 RA1/ICSPCLK RC5 2 14 RA2 RC4 3 13 RC0 RC3 4 12 RC1 RC6 5 11 RC2 6 7 8 9 10 7 7 6 5 4 RC RB RB RB RB
Note:
It is recommended that the exposed bottom pad be connected to VSS. See Table 4 for more information. © 2019 Microchip Technology Inc.
Datasheet
DS40002000B-page 7 Document Outline Description Core Features Memory Operating Characteristics eXtreme Low-Power (XLP) Features Power-Saving Operation Modes Digital Peripherals Analog Peripherals Flexible Oscillator Structure PIC16(L)F184XX Family Types Packages Pin Diagrams 1. 14/16-Pin Diagrams 2. 20-Pin Diagrams Pin Allocation Tables Table of Contents 1. Device Overview 1.1. New Core Features 1.1.1. XLP Technology 1.1.2. Multiple Oscillator Options and Features 1.2. Other Special Features 1.3. Details on Individual Family Members 1.4. Register and Bit Naming Conventions 1.4.1. Register Names 1.4.2. Bit Names 1.4.2.1. Short Bit Names 1.4.2.2. Long Bit Names 1.4.2.3. Bit Fields 1.4.3. Register and Bit Naming Exceptions 1.4.3.1. Status, Interrupt, and Mirror Bits 1.4.3.2. Legacy Peripherals 1.5. Register Legend 2. Guidelines for Getting Started with PIC16(L)F18424/44 Microcontrollers 2.1. Basic Connection Requirements 2.2. Power Supply Pins 2.2.1. Decoupling Capacitors 2.2.2. Tank Capacitors 2.3. Master Clear (MCLR) Pin 2.4. In-Circuit Serial Programming™ (ICSP™) Pins 2.5. External Oscillator Pins 2.6. Unused I/Os 3. Enhanced Mid-Range CPU 3.1. Automatic Interrupt Context Saving 3.2. 16-Level Stack with Overflow and Underflow 3.3. File Select Registers 3.4. Instruction Set 4. Device Configuration 4.1. Configuration Words 4.2. Code Protection 4.3. Write Protection 4.4. User ID 4.5. Device ID and Revision ID 4.6. Register Summary - Configuration Words 4.7. Register Definitions: Configuration Words 4.7.1. CONFIG1 4.7.2. CONFIG2 4.7.3. CONFIG3 4.7.4. CONFIG4 4.7.5. CONFIG5 4.8. Register Summary - Device and Revision 4.9. Register Definitions: Device and Revision 4.9.1. REVISION ID 4.9.2. DEVICE ID 5. Memory Organization 5.1. Program Memory Organization 5.1.1. Reading Program Memory as Data 5.1.1.1. RETLW Instruction 5.1.1.2. Indirect Read with FSR 5.2. Memory Access Partition (MAP) 5.2.1. Application Block 5.2.2. Boot Block 5.2.3. Storage Area Flash 5.2.4. Memory Write Protection 5.2.5. Memory Violation 5.3. Data Memory Organization 5.3.1. Bank Selection 5.3.2. Core Registers 5.3.2.1. STATUS Register 5.3.3. Special Function Register 5.3.4. General Purpose RAM 5.3.5. Common RAM 5.4. PCL and PCLATH 5.4.1. Modifying PCL 5.4.2. Computed GOTO 5.4.3. Computed Function Calls 5.4.4. Branching 5.5. Stack 5.5.1. Accessing the Stack 5.6. Indirect Addressing 5.6.1. Traditional/Banked Data Memory 5.6.2. Linear Data Memory 5.6.3. Data EEPROM Memory 5.6.4. Program Flash Memory 5.7. Register Summary - Memory and Status 5.8. Register Definitions: Memory and Status 5.8.1. INDF0 5.8.2. INDF1 5.8.3. PCL 5.8.4. STATUS 5.8.5. FSR0 5.8.6. FSR1 5.8.7. BSR 5.8.8. WREG 5.8.9. PCLATH 5.8.10. INTCON 5.8.11. TOS 5.8.12. STKPTR 5.9. Register Summary: Shadow Registers 5.10. Register Definitions: Shadow Registers 5.10.1. STATUS_SHAD 5.10.2. WREG_SHAD 5.10.3. BSR_SHAD 5.10.4. PCLATH_SHAD 5.10.5. FSR_SHAD 5.11. Device Configuration Information 5.12. Device Information Area 5.12.1. Microchip Unique Identifier (MUI) 5.12.2. External Unique Identifier (EUI) 5.12.3. Analog-to-Digital Conversion Data of the Temperature Sensor 5.12.4. Fixed Voltage Reference Data 6. NVM - Nonvolatile Memory Control 6.1. Program Flash Memory 6.1.1. Program Memory Voltages 6.1.1.1. Programming Externally 6.1.1.2. Self-Programming 6.2. Data EEPROM 6.3. FSR and INDF Access 6.3.1. FSR Read 6.3.2. FSR Write 6.4. NVMREG Access 6.4.1. NVMREG Read Operation 6.4.2. NVM Unlock Sequence 6.4.3. NVMREG Write to EEPROM 6.4.4. NVMREG Erase of Program Memory 6.4.5. NVMREG Write to Program Memory 6.4.6. Modifying Flash Program Memory 6.4.7. NVMREG Access to Device Information Area, Device Configuration Area, User ID, Device ID, EEPROM, and Configuration Words 6.4.8. Write Verify 6.4.9. WRERR Bit 6.5. Register Summary: NVM Control 6.6. Register Definitions: Nonvolatile Memory 6.6.1. NVMADR 6.6.2. NVMDAT 6.6.3. NVMCON1 6.6.4. NVMCON2 7. Interrupts 7.1. Operation 7.2. Interrupt Latency 7.3. Interrupts During Sleep 7.4. INT Pin 7.5. Automatic Context Saving 7.6. Register Summary - Interrupt Control 7.7. Register Definitions: Interrupt Control 7.7.1. INTCON 7.7.2. PIE0 7.7.3. PIE1 7.7.4. PIE2 7.7.5. PIE3 7.7.6. PIE4 7.7.7. PIE5 7.7.8. PIE6 7.7.9. PIE7 7.7.10. PIE8 7.7.11. PIR0 7.7.12. PIR1 7.7.13. PIR2 7.7.14. PIR3 7.7.15. PIR4 7.7.16. PIR5 7.7.17. PIR6 7.7.18. PIR7 7.7.19. PIR8 8. OSC - Oscillator Module 8.1. Overview 8.2. Clock Source Types 8.2.1. External Clock Sources 8.2.1.1. EC Mode 8.2.1.2. LP, XT, HS Modes 8.2.1.3. Oscillator Start-up Timer (OST) 8.2.1.4. 4x PLL 8.2.1.5. Secondary Oscillator 8.2.2. Internal Clock Sources 8.2.2.1. HFINTOSC 8.2.2.2. MFINTOSC 8.2.2.3. 2x PLL 8.2.2.4. Internal Oscillator Frequency Adjustment 8.2.2.5. LFINTOSC 8.2.2.6. Oscillator Status and Manual Enable 8.2.2.7. HFOR and MFOR Bits 8.3. Clock Switching 8.3.1. New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) Bits 8.3.2. PLL Input Switch 8.3.3. Clock Switch and Sleep 8.4. Fail-Safe Clock Monitor 8.4.1. Fail-Safe Detection 8.4.2. Fail-Safe Operation 8.4.3. Fail-Safe Condition Clearing 8.4.4. Reset or Wake-up from Sleep 8.5. Register Summary - OSC 8.6. Register Definitions: Oscillator Control 8.6.1. OSCCON1 8.6.2. OSCCON2 8.6.3. OSCCON3 8.6.4. OSCSTAT 8.6.5. OSCEN 8.6.6. OSCTUNE 8.6.7. OSCFRQ 9. REFCLK - Reference Clock Output Module 9.1. Clock Source 9.1.1. Clock Synchronization 9.2. Programmable Clock Divider 9.3. Selectable Duty Cycle 9.4. Operation in Sleep Mode 9.5. Register Summary: Reference CLK 9.6. Register Definitions: Reference Clock 9.6.1. CLKRCON 9.6.2. CLKRCLK 10. Resets 10.1. Power-on Reset (POR) 10.2. Brown-out Reset (BOR) 10.2.1. BOR is Always ON 10.2.2. BOR is OFF in Sleep 10.2.3. BOR Controlled by Software 10.2.4. BOR is Always OFF 10.3. Low-Power Brown-out Reset (LPBOR) 10.3.1. Enabling LPBOR 10.3.2. LPBOR Module Output 10.4. MCLR Reset 10.4.1. MCLR Enabled 10.4.2. MCLR Disabled 10.5. Windowed Watchdog Timer (WWDT) Reset 10.6. RESET Instruction 10.7. Stack Overflow/Underflow Reset 10.8. Programming Mode Exit 10.9. Power-up Timer (PWRT) 10.10. Start-up Sequence 10.11. Memory Execution Violation 10.12. Determining the Cause of a Reset 10.13. Register Summary - BOR Control and Power Control 10.14. Register Definitions: Power Control 10.14.1. BORCON 10.14.2. PCON0 10.14.3. PCON1 11. WWDT - Windowed Watchdog Timer 11.1. Independent Clock Source 11.2. WWDT Operating Modes 11.3. Time-out Period 11.4. Watchdog Window 11.5. Clearing the WWDT 11.5.1. CLRWDT Considerations (Windowed Mode) 11.6. Operation During Sleep 11.7. Register Summary - WDT Control 11.8. Register Definitions: Windowed Watchdog Timer Control 11.8.1. WDTCON0 11.8.2. WDTCON1 11.8.3. WDTPSL 11.8.4. WDTPSH 11.8.5. WDTTMR 12. Power-Saving Operation Modes 12.1. Doze Mode 12.1.1. Doze Operation 12.1.2. Interrupts During Doze 12.2. Sleep Mode 12.2.1. Wake-up from Sleep 12.2.2. Wake-up Using Interrupts 12.2.3. Low-Power Sleep Mode 12.2.3.1. Sleep Current vs. Wake-up Time 12.2.3.2. Peripheral Usage in Sleep 12.3. Idle Mode 12.3.1. Idle and Interrupts 12.3.2. Idle and WWDT 12.4. Register Summary - Power Savings Control 12.5. Register Definitions: Power Savings Control 12.5.1. VREGCON 12.5.2. CPUDOZE 13. PMD - Peripheral Module Disable 13.1. Disabling a Module 13.2. Enabling a Module 13.3. System Clock Disable 13.4. Register Summary - PMD 13.5. Register Definitions: Peripheral Module Disable 13.5.1. PMD0 13.5.2. PMD1 13.5.3. PMD2 13.5.4. PMD3 13.5.5. PMD4 13.5.6. PMD5 13.5.7. PMD6 13.5.8. PMD7 14. I/O Ports 14.1. PORT Availability 14.2. I/O Ports Description 14.3. I/O Priorities 14.4. PORTx Registers 14.4.1. Data Register 14.4.2. Direction Control 14.4.3. Open-Drain Control 14.4.4. Slew Rate Control 14.4.5. Input Threshold Control 14.4.6. Analog Control 14.4.7. Weak Pull-up Control 14.4.8. PORTx Functions and Output Priorities 14.4.9. MCLR/VPP Pin 14.5. Register Summary - Input/Output 14.6. Register Definitions: Port Control 14.6.1. PORTA 14.6.2. PORTB 14.6.3. PORTC 14.6.4. TRISA 14.6.5. TRISB 14.6.6. TRISC 14.6.7. LATA 14.6.8. LATB 14.6.9. LATC 14.6.10. ANSELA 14.6.11. ANSELB 14.6.12. ANSELC 14.6.13. WPUA 14.6.14. WPUB 14.6.15. WPUC 14.6.16. ODCONA 14.6.17. ODCONB 14.6.18. ODCONC 14.6.19. SLRCONA 14.6.20. SLRCONB 14.6.21. SLRCONC 14.6.22. INLVLA 14.6.23. INLVLB 14.6.24. INLVLC 15. IOC - Interrupt-On-Change 15.1. Enabling the Module 15.2. Individual Pin Configuration 15.3. Interrupt Flags 15.3.1. Clearing Interrupt Flags 15.4. Operation in Sleep 15.5. Register Summary - Interrupt-on-Change 15.6. Register Definitions: Interrupt-on-Change Control 15.6.1. IOCAP 15.6.2. IOCAN 15.6.3. IOCAF 15.6.4. IOCBP 15.6.5. IOCBN 15.6.6. IOCBF 15.6.7. IOCCP 15.6.8. IOCCN 15.6.9. IOCCF 16. PPS - Peripheral Pin Select Module 16.1. PPS Inputs 16.2. PPS Outputs 16.3. Bidirectional Pins 16.4. PPS Lock 16.5. PPS1WAY Bit 16.6. Operation During Sleep 16.7. Effects of a Reset 16.8. Register Summary - PPS 16.9. Register Definitions: PPS Input and Output Selection 16.9.1. PPS Lock Register 16.9.2. Peripheral xxx Input Selection 16.9.3. Pin Rxy Output Source Selection Register 17. CLC - Configurable Logic Cell 17.1. CLC Setup 17.1.1. Data Selection 17.1.2. Data Gating 17.1.3. Logic Function 17.1.4. Output Polarity 17.2. CLC Interrupts 17.3. Output Mirror Copies 17.4. Effects of a Reset 17.5. Operation During Sleep 17.6. CLC Setup Steps 17.7. Register Summary - CLC Control 17.8. Register Definitions: Configurable Logic Cell 17.8.1. CLCDATA 17.8.2. CLCxCON 17.8.3. CLCxPOL 17.8.4. CLCxSEL0 17.8.5. CLCxSEL1 17.8.6. CLCxSEL2 17.8.7. CLCxSEL3 17.8.8. CLCxGLS0 17.8.9. CLCxGLS1 17.8.10. CLCxGLS2 17.8.11. CLCxGLS3 18. TMR0 - Timer0 Module 18.1. Timer0 Operation 18.1.1. 8-bit Mode 18.1.2. 16-Bit Mode 18.2. Clock Selection 18.2.1. Clock Source Selection 18.2.2. Synchronous Mode 18.2.3. Asynchronous Mode 18.2.4. Programmable Prescaler 18.3. Timer0 Output and Interrupt 18.3.1. Programmable Postscaler 18.3.2. Timer0 Output 18.3.3. Timer0 Interrupt 18.3.4. Timer0 Example 18.4. Operation During Sleep 18.5. Register Summary - Timer0 18.6. Register Definitions: Timer0 Control 18.6.1. TMR0L 18.6.2. TMR0H 18.6.3. T0CON0 18.6.4. T0CON1 19. TMR1 - Timer1 Module with Gate Control 19.1. Timer1 Operation 19.2. Clock Source Selection 19.2.1. Internal Clock Source 19.2.2. External Clock Source 19.3. Timer1 Prescaler 19.4. Secondary Oscillator 19.5. Timer1 Operation in Asynchronous Counter Mode 19.5.1. Reading and Writing Timer1 in Asynchronous Counter Mode 19.6. Timer1 16-Bit Read/Write Mode 19.7. Timer1 Gate 19.7.1. Timer1 Gate Enable 19.7.2. Timer1 Gate Source Selection 19.7.3. Timer1 Gate Toggle Mode 19.7.4. Timer1 Gate Single Pulse Mode 19.7.5. Timer1 Gate Value Status 19.7.6. Timer1 Gate Event Interrupt 19.8. Timer1 Interrupt 19.9. Timer1 Operation During Sleep 19.10. CCP Capture/Compare Time Base 19.11. CCP Special Event Trigger 19.12. Peripheral Module Disable 19.13. Register Summary - Timer1 19.14. Register Definitions: Timer1 19.14.1. Timer Register 19.14.2. TxCON 19.14.3. TxGCON 19.14.4. TMRxGATE 19.14.5. TMRxCLK 20. TMR2 - Timer2 Module 20.1. Timer2 Operation 20.1.1. Free-Running Period Mode 20.1.2. One-Shot Mode 20.1.3. Monostable Mode 20.2. Timer2 Output 20.3. External Reset Sources 20.4. Timer2 Interrupt 20.5. PSYNC bit 20.6. CSYNC bit 20.7. Operating Modes 20.8. Operation Examples 20.8.1. Software Gate Mode 20.8.2. Hardware Gate Mode 20.8.3. Edge-Triggered Hardware Limit Mode 20.8.4. Level-Triggered Hardware Limit Mode 20.8.5. Software Start One-Shot Mode 20.8.6. Edge-Triggered One-Shot Mode 20.8.7. Edge-Triggered Hardware Limit One-Shot Mode 20.8.8. Level Reset, Edge-Triggered Hardware Limit One-Shot Modes 20.8.9. Edge-Triggered Monostable Modes 20.8.10. Level-Triggered Hardware Limit One-Shot Modes 20.9. Timer2 Operation During Sleep 20.10. Register Summary - Timer2 20.11. Register Definitions: Timer2 Control 20.11.1. TxTMR 20.11.2. TxPR 20.11.3. TxCON 20.11.4. TxHLT 20.11.5. TxCLKCON 20.11.6. TxRST 21. SMT - Signal Measurement Timer 21.1. SMT Operation 21.1.1. Clock Source Selection 21.1.2. Signal and Window Source Selection 21.1.3. Time Base 21.1.4. Capture Pulse Width and Period Registers 21.1.5. Status Information 21.1.6. Modes of Operation 21.1.6.1. Timer Mode 21.1.6.2. Gated Timer Mode 21.1.6.3. Period and Duty Cycle Measurement Mode 21.1.6.4. High and Low Measurement Mode 21.1.6.5. Windowed Measurement Mode 21.1.6.6. Gated Window Measurement Mode 21.1.6.7. Time of Flight Measurement Mode 21.1.6.8. Capture Mode 21.1.6.9. Counter Mode 21.1.6.10. Gated Counter Mode 21.1.6.11. Windowed Counter Mode 21.1.7. Interrupts 21.1.8. Operation During Sleep 21.2. Register Summary - SMT Control 21.3. Register Definitions: SMT Control 21.3.1. SMTxTMR 21.3.2. SMTxCPR 21.3.3. SMTxCPW 21.3.4. SMTxPR 21.3.5. SMTxCON0 21.3.6. SMTxCON1 21.3.7. SMTxSTAT 21.3.8. SMTxCLK 21.3.9. SMTxSIG 21.3.10. SMTxWIN 22. Capture/Compare/PWM Module 22.1. CCP Module Configuration 22.1.1. CCP Modules and Timer Resources 22.1.2. Open-Drain Output Option 22.2. Capture Mode 22.2.1. Capture Sources 22.2.2. Timer1 Mode Resource 22.2.3. Software Interrupt Mode 22.2.4. CCP Prescaler 22.2.5. Capture During Sleep 22.3. Compare Mode 22.3.1. CCPx Pin Configuration 22.3.2. Timer1 Mode Resource 22.3.3. Auto-Conversion Trigger 22.3.4. Compare During Sleep 22.4. PWM Overview 22.4.1. Standard PWM Operation 22.4.2. Setup for PWM Operation 22.4.3. Timer2 Timer Resource 22.4.4. PWM Period 22.4.5. PWM Duty Cycle 22.4.6. PWM Resolution 22.4.7. Operation in Sleep Mode 22.4.8. Changes in System Clock Frequency 22.4.9. Effects of Reset 22.5. Register Summary - CCP Control 22.6. Register Definitions: CCP Control 22.6.1. CCPxCON 22.6.2. CCPxCAP 22.6.3. CCPRx 23. CCP/PWM Timer Resource Selection 23.1. Register Summary - Timer Selection Registers for CCP/PWM 23.2. Register Definitions: CCP/PWM Timer Selection 23.2.1. CCPTMRS0 23.2.2. CCPTMRS1 24. PWM - Pulse-Width Modulation 24.1. Fundamental Operation 24.2. PWM Output Polarity 24.3. PWM Period 24.4. PWM Duty Cycle 24.5. PWM Resolution 24.6. Operation in Sleep Mode 24.7. Changes in System Clock Frequency 24.8. Effects of Reset 24.9. Setup for PWM Operation using PWMx Output Pins 24.9.1. PWMx Pin Configuration 24.10. Setup for PWM Operation to Other Device Peripherals 24.11. Register Summary - Registers Associated with PWM 24.12. Register Definitions: PWM Control 24.12.1. PWMxDC 24.12.2. PWMxCON 25. CWG - Complementary Waveform Generator 25.1. Fundamental Operation 25.2. Operating Modes 25.2.1. Half-Bridge Mode 25.2.2. Push-Pull Mode 25.2.3. Full-Bridge Modes 25.2.3.1. Direction Change in Full-Bridge Mode 25.2.3.2. Dead-Band Delay in Full-Bridge Mode 25.2.4. Steering Modes 25.2.4.1. Synchronous Steering Mode 25.2.4.2. Asynchronous Steering Mode 25.3. Start-up Considerations 25.4. Clock Source 25.5. Selectable Input Sources 25.6. Output Control 25.6.1. CWG Outputs 25.6.2. Polarity Control 25.7. Dead-Band Control 25.7.1. Dead-Band Functionality in Half-Bridge mode 25.7.2. Dead-Band Functionality in Full-Bridge mode 25.8. Rising Edge and Reverse Dead Band 25.9. Falling Edge and Forward Dead Band 25.10. Dead-Band Jitter 25.11. Auto-Shutdown 25.11.1. Shutdown 25.11.1.1. Software Generated Shutdown 25.11.1.2. External Input Source 25.11.1.3. Pin Override Levels 25.11.1.4. Auto-Shutdown Interrupts 25.11.2. Auto-Shutdown Restart 25.11.2.1. Software-Controlled Restart 25.11.2.2. Auto-Restart 25.12. Operation During Sleep 25.13. Configuring the CWG 25.14. Register Summary - CWG Control 25.15. Register Definitions: CWG Control 25.15.1. CWGxCLK 25.15.2. CWGxISM 25.15.3. CWGxDBR 25.15.4. CWGxDBF 25.15.5. CWGxCON0 25.15.6. CWGxCON1 25.15.7. CWGxAS0 25.15.8. CWGxAS1 25.15.9. CWGxSTR 26. NCO - Numerically Controlled Oscillator 26.1. NCO Operation 26.1.1. NCO Clock Sources 26.1.2. Accumulator 26.1.3. Adder 26.1.4. Increment Registers 26.2. Fixed Duty Cycle Mode 26.3. Pulse Frequency Mode 26.3.1. Output Pulse Width Control 26.4. Output Polarity Control 26.5. Interrupts 26.6. Effects of a Reset 26.7. Operation in Sleep 26.8. Register Summary - NCO 26.9. Register Definitions: NCO 26.9.1. NCOxACC 26.9.2. NCOxINC 26.9.3. NCOxCON 26.9.4. NCOxCLK 27. DSM - Data Signal Modulator Module 27.1. DSM Operation 27.2. Modulator Signal Sources 27.3. Carrier Signal Sources 27.4. Carrier Synchronization 27.5. Carrier Source Polarity Select 27.6. Programmable Modulator Data 27.7. Modulated Output Polarity 27.8. Operation in Sleep Mode 27.9. Effects of a Reset 27.10. Peripheral Module Disable 27.11. Register Summary - DSM 27.12. Register Definitions: Modulation Control 27.12.1. MDxCON0 27.12.2. MDxCON1 27.12.3. MDxSRC 27.12.4. MDxCARL 27.12.5. MDxCARH 28. EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter 28.1. EUSART Asynchronous Mode 28.1.1. EUSART Asynchronous Transmitter 28.1.1.1. Enabling the Transmitter 28.1.1.2. Transmitting Data 28.1.1.3. Transmit Data Polarity 28.1.1.4. Transmit Interrupt Flag 28.1.1.5. TSR Status 28.1.1.6. Transmitting 9-Bit Characters 28.1.1.7. Asynchronous Transmission Setup 28.1.2. EUSART Asynchronous Receiver 28.1.2.1. Enabling the Receiver 28.1.2.2. Receiving Data 28.1.2.3. Receive Interrupts 28.1.2.4. Receive Framing Error 28.1.2.5. Receive Overrun Error 28.1.2.6. Receiving 9-Bit Characters 28.1.2.7. Address Detection 28.1.2.8. Asynchronous Reception Setup 28.1.2.9. 9-Bit Address Detection Mode Setup 28.1.3. Clock Accuracy with Asynchronous Operation 28.2. EUSART Baud Rate Generator (BRG) 28.2.1. Auto-Baud Detect 28.2.2. Auto-Baud Overflow 28.2.3. Auto-Wake-up on Break 28.2.3.1. Special Considerations 28.2.4. Break Character Sequence 28.2.4.1. Break and Sync Transmit Sequence 28.2.5. Receiving a Break Character 28.3. EUSART Synchronous Mode 28.3.1. Synchronous Master Mode 28.3.1.1. Master Clock 28.3.1.2. Clock Polarity 28.3.1.3. Synchronous Master Transmission 28.3.1.4. Synchronous Master Transmission Setup 28.3.1.5. Synchronous Master Reception 28.3.1.6. Receive Overrun Error 28.3.1.7. Receiving 9-Bit Characters 28.3.1.8. Synchronous Master Reception Setup 28.3.2. Synchronous Slave Mode 28.3.2.1. Slave Clock 28.3.2.2. EUSART Synchronous Slave Transmit 28.3.2.3. Synchronous Slave Transmission Setup 28.3.2.4. EUSART Synchronous Slave Reception 28.3.2.5. Synchronous Slave Reception Setup: 28.4. EUSART Operation During Sleep 28.4.1. Synchronous Receive During Sleep 28.4.2. Synchronous Transmit During Sleep 28.5. Register Summary - EUSART 28.6. Register Definitions: EUSART Control 28.6.1. RCxREG 28.6.2. TXxREG 28.6.3. SPxBRG 28.6.4. RCxSTA 28.6.5. TXxSTA 28.6.6. BAUDxCON 29. MSSP - Master Synchronous Serial Port Module 29.1. SPI Mode Overview 29.1.1. SPI Mode Registers 29.2. SPI Mode Operation 29.2.1. SPI Master Mode 29.2.2. SPI Slave Mode 29.2.3. Daisy-Chain Configuration 29.2.4. Slave Select Synchronization 29.2.5. SPI Operation in Sleep Mode 29.3. I2C Mode Overview 29.3.1. Register Definitions: I2C Mode 29.4. I2C Mode Operation 29.4.1. Clock Stretching 29.4.2. Arbitration 29.4.3. Byte Format 29.4.4. Definition of I2C Terminology 29.4.5. SDA and SCL Pins 29.4.6. SDA Hold Time 29.4.7. Start Condition 29.4.8. Stop Condition 29.4.9. Restart Condition 29.4.10. Start/Stop Condition Interrupt Masking 29.4.11. Acknowledge Sequence 29.5. I2C Slave Mode Operation 29.5.1. Slave Mode Addresses 29.5.1.1. I2C Slave 7-bit Addressing Mode 29.5.1.2. I2C Slave 10-bit Addressing Mode 29.5.2. Slave Reception 29.5.2.1. 7-bit Addressing Reception 29.5.2.2. 7-bit Reception with AHEN and DHEN 29.5.3. Slave Transmission 29.5.3.1. Slave Mode Bus Collision 29.5.3.2. 7-bit Transmission 29.5.3.3. 7-bit Transmission with Address Hold Enabled 29.5.4. Slave Mode 10-bit Address Reception 29.5.5. 10-bit Addressing with Address or Data Hold 29.5.6. Clock Stretching 29.5.6.1. Normal Clock Stretching 29.5.6.2. 10-bit Addressing Mode 29.5.6.3. Byte NACKing 29.5.7. Clock Synchronization and the CKP bit 29.5.8. General Call Address Support 29.5.9. SSP Mask Register 29.6. I2C Master Mode 29.6.1. I2C Master Mode Operation 29.6.2. Clock Arbitration 29.6.3. WCOL Status Flag 29.6.4. I2C Master Mode Start Condition Timing 29.6.5. I2C Master Mode Repeated Start Condition Timing 29.6.6. I2C Master Mode Transmission 29.6.6.1. BF Status Flag 29.6.6.2. WCOL Status Flag 29.6.6.3. ACKSTAT Status Flag 29.6.6.4. Typical Transmit Sequence: 29.6.7. I2C Master Mode Reception 29.6.7.1. BF Status Flag 29.6.7.2. SSPOV Status Flag 29.6.7.3. WCOL Status Flag 29.6.7.4. Typical Receive Sequence: 29.6.8. Acknowledge Sequence Timing 29.6.8.1. Acknowledge Write Collision 29.6.9. Stop Condition Timing 29.6.9.1. Write Collision on Stop 29.6.10. Sleep Operation 29.6.11. Effects of a Reset 29.6.12. Multi-Master Mode 29.6.13. Multi-Master Communication, Bus Collision and Bus Arbitration 29.6.13.1. Bus Collision During a Start Condition 29.6.13.2. Bus Collision During a Repeated Start Condition 29.6.13.3. Bus Collision During a Stop Condition 29.7. Baud Rate Generator 29.8. Register Summary: MSSP Control 29.9. Register Definitions: MSSP Control 29.9.1. SSPxBUF 29.9.2. SSPxADD 29.9.3. SSPxMSK 29.9.4. SSPxSTAT 29.9.5. SSPxCON1 29.9.6. SSPxCON2 29.9.7. SSPxCON3 30. FVR - Fixed Voltage Reference 30.1. Independent Gain Amplifiers 30.2. FVR Stabilization Period 30.3. Register Summary - FVR 30.4. Register Definitions: FVR Control 30.4.1. FVRCON 31. Temperature Indicator Module 31.1. Module Operation 31.2. Minimum Operating VDD 31.3. Temperature Indicator Range 31.4. Estimation of Temperature 31.4.1. Calibration 31.4.1.1. Higher-Order Calibration 31.4.2. Temperature Resolution 31.5. ADC Acquisition Time 32. ADC2 - Analog-to-Digital Converter 32.1. ADC Configuration 32.1.1. Port Configuration 32.1.2. Channel Selection 32.1.3. ADC Voltage Reference 32.1.4. Conversion Clock 32.1.5. Interrupts 32.1.6. Result Formatting 32.2. ADC Operation 32.2.1. Starting a Conversion 32.2.2. Completion of a Conversion 32.2.3. Terminating a Conversion 32.2.4. ADC Operation During Sleep 32.2.5. External Trigger During Sleep 32.2.6. Auto-Conversion Trigger 32.2.7. ADC Conversion Procedure (Basic Mode) 32.3. ADC Acquisition Requirements 32.4. ADC Charge Pump 32.5. Capacitive Voltage Divider (CVD) Features 32.5.1. CVD Operation 32.5.2. Precharge Control 32.5.3. Acquisition Control for CVD 32.5.4. Guard Ring Outputs 32.5.5. Additional Sample and Hold Capacitance 32.6. Computation Operation 32.6.1. Digital Filter/Average 32.6.2. Basic Mode 32.6.3. Accumulate Mode 32.6.4. Average Mode 32.6.5. Burst Average Mode 32.6.6. Low-pass Filter Mode 32.6.7. Threshold Comparison 32.6.8. Continuous Sampling Mode 32.6.9. Double Sample Conversion 32.7. Register Summary - ADC Control 32.8. Register Definitions: ADC Control 32.8.1. ADLTH 32.8.2. ADUTH 32.8.3. ADERR 32.8.4. ADSTPT 32.8.5. ADFLTR 32.8.6. ADACC 32.8.7. ADCNT 32.8.8. ADRPT 32.8.9. ADPREV 32.8.10. ADRES 32.8.11. ADPCH 32.8.12. ADACQ 32.8.13. ADCAP 32.8.14. ADPRE 32.8.15. ADCON0 32.8.16. ADCON1 32.8.17. ADCON2 32.8.18. ADCON3 32.8.19. ADSTAT 32.8.20. ADREF 32.8.21. ADACT 32.8.22. ADCLK 32.8.23. ADCPCON0 33. DAC - 5-Bit Digital-to-Analog Converter 33.1. Output Voltage Selection 33.2. Ratiometric Output Level 33.3. DAC Voltage Reference Output 33.4. Operation During Sleep 33.5. Effects of a Reset 33.6. Register Summary - DAC Control 33.7. Register Definitions: DAC Control 33.7.1. DAC1CON0 33.7.2. DAC1CON1 34. CMP - Comparator Module 34.1. Comparator Overview 34.2. Comparator Control 34.2.1. Comparator Enable 34.2.2. Comparator Output 34.2.3. Comparator Output Polarity 34.3. Comparator Hysteresis 34.4. Operation With Timer1 Gate 34.4.1. Comparator Output Synchronization 34.5. Comparator Interrupt 34.6. Comparator Positive Input Selection 34.7. Comparator Negative Input Selection 34.8. Comparator Response Time 34.9. Analog Input Connection Considerations 34.10. CWG1 Auto-Shutdown Source 34.11. ADC Auto-Trigger Source 34.12. Even Numbered Timers Reset 34.13. Operation in Sleep Mode 34.14. Register Summary - Comparator 34.15. Register Definitions: Comparator Control 34.15.1. CMOUT 34.15.2. CMxCON0 34.15.3. CMxCON1 34.15.4. CMxNCH 34.15.5. CMxPCH 35. ZCD - Zero-Cross Detection Module 35.1. External Resistor Selection 35.2. ZCD Logic Output 35.3. ZCD Logic Polarity 35.4. ZCD Interrupts 35.5. Correction for ZCPINV Offset 35.5.1. Correction by AC Coupling 35.5.2. Correction By Offset Current 35.6. Handling VPEAK Variations 35.7. Operation During Sleep 35.8. Effects of a Reset 35.9. Disabling the ZCD Module 35.10. Register Summary: ZCD Control 35.11. Register Definitions: ZCD Control 35.11.1. ZCDCON 36. Register Summary 37. Instruction Set Summary 37.1. Read-Modify-Write Operations 37.2. Standard Instruction Set 37.2.1. Standard Instruction Set 38. ICSP™ - In-Circuit Serial Programming™ 38.1. High-Voltage Programming Entry Mode 38.2. Low-Voltage Programming Entry Mode 38.3. Common Programming Interfaces 39. Development Support 39.1. MPLAB X Integrated Development Environment Software 39.2. MPLAB XC Compilers 39.3. MPASM Assembler 39.4. MPLINK Object Linker/MPLIB Object Librarian 39.5. MPLAB Assembler, Linker and Librarian for Various Device Families 39.6. MPLAB X SIM Software Simulator 39.7. MPLAB REAL ICE In-Circuit Emulator System 39.8. MPLAB ICD 3 In-Circuit Debugger System 39.9. PICkit 3 In-Circuit Debugger/Programmer 39.10. MPLAB PM3 Device Programmer 39.11. Demonstration/Development Boards, Evaluation Kits, and Starter Kits 39.12. Third-Party Development Tools 40. Electrical Specifications 40.1. Absolute Maximum Ratings(†) 40.2. Standard Operating Conditions 40.3. DC Characteristics 40.3.1. Supply Voltage 40.3.2. Supply Current (IDD)(1,2,4) 40.3.3. Power-Down Current (IPD)(1,2) 40.3.4. I/O Ports 40.3.5. Memory Programming Specifications 40.3.6. Thermal Characteristics 40.4. AC Characteristics 40.4.1. External Clock/Oscillator Timing Requirements 40.4.2. Internal Oscillator Parameters(1) 40.4.3. PLL Specifications 40.4.4. I/O and CLKOUT Timing Specifications 40.4.5. Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications 40.4.6. Temperature Indicator Requirements 40.4.7. Analog-to-Digital Converter (ADC) Accuracy Specifications(1,2) 40.4.8. Analog-to-Digital Converter (ADC) Conversion Timing Specifications 40.4.9. Comparator Specifications 40.4.10. 5-Bit DAC Specifications 40.4.11. Fixed Voltage Reference (FVR) Specifications 40.4.12. Zero-Cross Detect (ZCD) Specifications 40.4.13. Timer0 and Timer1 External Clock Requirements 40.4.14. Capture/Compare/PWM Requirements (CCP) 40.4.15. Configurable Logic Cell (CLC) Characteristics 40.4.16. EUSART Synchronous Transmission Requirements 40.4.17. EUSART Synchronous Receive Requirements 40.4.18. SPI Mode Requirements 40.4.19. I2C Bus Start/Stop Bits Requirements 40.4.20. I2C Bus Data Requirements 41. DC and AC Characteristics Graphs and Tables 41.1. Graphs 42. Packaging Information 42.1. Package Details 43. Revision History The Microchip Website Product Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service
PIC16(L)F18424/44 20-Pin Diagrams Figure 3. 20-Pin PDIP, SOIC, SSOP
Rev. 00-000020A 6/21/2017 VDD 1 20 VSS RA5 2 19 RA0/ICSPDAT RA4 3 18 RA1/ICSPCLK MCLR/VPP/RA3 4 17 RA2 RC5 5 16 RC0 RC4 6 15 RC1 RC3 7 14 RC2 RC6 8 13 RB4 RC7 9 12 RB5 RB7 10 11 RB6
Figure 4. 20-Pin UQFN (4x4)
Rev. 00-000020B 6/21/2016 T DA P ICS 4 5 D S 0/ D S RA RA V V RA 20 19 18 17 16 MCLR/VPP/RA3 1 15 RA1/ICSPCLK RC5 2 14 RA2 RC4 3 13 RC0 RC3 4 12 RC1 RC6 5 11 RC2 6 7 8 9 10 7 7 6 5 4 RC RB RB RB RB
Note:
It is recommended that the exposed bottom pad be connected to VSS. See Table 4 for more information. © 2019 Microchip Technology Inc.
Datasheet
DS40002000B-page 7 Document Outline Description Core Features Memory Operating Characteristics eXtreme Low-Power (XLP) Features Power-Saving Operation Modes Digital Peripherals Analog Peripherals Flexible Oscillator Structure PIC16(L)F184XX Family Types Packages Pin Diagrams 1. 14/16-Pin Diagrams 2. 20-Pin Diagrams Pin Allocation Tables Table of Contents 1. Device Overview 1.1. New Core Features 1.1.1. XLP Technology 1.1.2. Multiple Oscillator Options and Features 1.2. Other Special Features 1.3. Details on Individual Family Members 1.4. Register and Bit Naming Conventions 1.4.1. Register Names 1.4.2. Bit Names 1.4.2.1. Short Bit Names 1.4.2.2. Long Bit Names 1.4.2.3. Bit Fields 1.4.3. Register and Bit Naming Exceptions 1.4.3.1. Status, Interrupt, and Mirror Bits 1.4.3.2. Legacy Peripherals 1.5. Register Legend 2. Guidelines for Getting Started with PIC16(L)F18424/44 Microcontrollers 2.1. Basic Connection Requirements 2.2. Power Supply Pins 2.2.1. Decoupling Capacitors 2.2.2. Tank Capacitors 2.3. Master Clear (MCLR) Pin 2.4. In-Circuit Serial Programming™ (ICSP™) Pins 2.5. External Oscillator Pins 2.6. Unused I/Os 3. Enhanced Mid-Range CPU 3.1. Automatic Interrupt Context Saving 3.2. 16-Level Stack with Overflow and Underflow 3.3. File Select Registers 3.4. Instruction Set 4. Device Configuration 4.1. Configuration Words 4.2. Code Protection 4.3. Write Protection 4.4. User ID 4.5. Device ID and Revision ID 4.6. Register Summary - Configuration Words 4.7. Register Definitions: Configuration Words 4.7.1. CONFIG1 4.7.2. CONFIG2 4.7.3. CONFIG3 4.7.4. CONFIG4 4.7.5. CONFIG5 4.8. Register Summary - Device and Revision 4.9. Register Definitions: Device and Revision 4.9.1. REVISION ID 4.9.2. DEVICE ID 5. Memory Organization 5.1. Program Memory Organization 5.1.1. Reading Program Memory as Data 5.1.1.1. RETLW Instruction 5.1.1.2. Indirect Read with FSR 5.2. Memory Access Partition (MAP) 5.2.1. Application Block 5.2.2. Boot Block 5.2.3. Storage Area Flash 5.2.4. Memory Write Protection 5.2.5. Memory Violation 5.3. Data Memory Organization 5.3.1. Bank Selection 5.3.2. Core Registers 5.3.2.1. STATUS Register 5.3.3. Special Function Register 5.3.4. General Purpose RAM 5.3.5. Common RAM 5.4. PCL and PCLATH 5.4.1. Modifying PCL 5.4.2. Computed GOTO 5.4.3. Computed Function Calls 5.4.4. Branching 5.5. Stack 5.5.1. Accessing the Stack 5.6. Indirect Addressing 5.6.1. Traditional/Banked Data Memory 5.6.2. Linear Data Memory 5.6.3. Data EEPROM Memory 5.6.4. Program Flash Memory 5.7. Register Summary - Memory and Status 5.8. Register Definitions: Memory and Status 5.8.1. INDF0 5.8.2. INDF1 5.8.3. PCL 5.8.4. STATUS 5.8.5. FSR0 5.8.6. FSR1 5.8.7. BSR 5.8.8. WREG 5.8.9. PCLATH 5.8.10. INTCON 5.8.11. TOS 5.8.12. STKPTR 5.9. Register Summary: Shadow Registers 5.10. Register Definitions: Shadow Registers 5.10.1. STATUS_SHAD 5.10.2. WREG_SHAD 5.10.3. BSR_SHAD 5.10.4. PCLATH_SHAD 5.10.5. FSR_SHAD 5.11. Device Configuration Information 5.12. Device Information Area 5.12.1. Microchip Unique Identifier (MUI) 5.12.2. External Unique Identifier (EUI) 5.12.3. Analog-to-Digital Conversion Data of the Temperature Sensor 5.12.4. Fixed Voltage Reference Data 6. NVM - Nonvolatile Memory Control 6.1. Program Flash Memory 6.1.1. Program Memory Voltages 6.1.1.1. Programming Externally 6.1.1.2. Self-Programming 6.2. Data EEPROM 6.3. FSR and INDF Access 6.3.1. FSR Read 6.3.2. FSR Write 6.4. NVMREG Access 6.4.1. NVMREG Read Operation 6.4.2. NVM Unlock Sequence 6.4.3. NVMREG Write to EEPROM 6.4.4. NVMREG Erase of Program Memory 6.4.5. NVMREG Write to Program Memory 6.4.6. Modifying Flash Program Memory 6.4.7. NVMREG Access to Device Information Area, Device Configuration Area, User ID, Device ID, EEPROM, and Configuration Words 6.4.8. Write Verify 6.4.9. WRERR Bit 6.5. Register Summary: NVM Control 6.6. Register Definitions: Nonvolatile Memory 6.6.1. NVMADR 6.6.2. NVMDAT 6.6.3. NVMCON1 6.6.4. NVMCON2 7. Interrupts 7.1. Operation 7.2. Interrupt Latency 7.3. Interrupts During Sleep 7.4. INT Pin 7.5. Automatic Context Saving 7.6. Register Summary - Interrupt Control 7.7. Register Definitions: Interrupt Control 7.7.1. INTCON 7.7.2. PIE0 7.7.3. PIE1 7.7.4. PIE2 7.7.5. PIE3 7.7.6. PIE4 7.7.7. PIE5 7.7.8. PIE6 7.7.9. PIE7 7.7.10. PIE8 7.7.11. PIR0 7.7.12. PIR1 7.7.13. PIR2 7.7.14. PIR3 7.7.15. PIR4 7.7.16. PIR5 7.7.17. PIR6 7.7.18. PIR7 7.7.19. PIR8 8. OSC - Oscillator Module 8.1. Overview 8.2. Clock Source Types 8.2.1. External Clock Sources 8.2.1.1. EC Mode 8.2.1.2. LP, XT, HS Modes 8.2.1.3. Oscillator Start-up Timer (OST) 8.2.1.4. 4x PLL 8.2.1.5. Secondary Oscillator 8.2.2. Internal Clock Sources 8.2.2.1. HFINTOSC 8.2.2.2. MFINTOSC 8.2.2.3. 2x PLL 8.2.2.4. Internal Oscillator Frequency Adjustment 8.2.2.5. LFINTOSC 8.2.2.6. Oscillator Status and Manual Enable 8.2.2.7. HFOR and MFOR Bits 8.3. Clock Switching 8.3.1. New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) Bits 8.3.2. PLL Input Switch 8.3.3. Clock Switch and Sleep 8.4. Fail-Safe Clock Monitor 8.4.1. Fail-Safe Detection 8.4.2. Fail-Safe Operation 8.4.3. Fail-Safe Condition Clearing 8.4.4. Reset or Wake-up from Sleep 8.5. Register Summary - OSC 8.6. Register Definitions: Oscillator Control 8.6.1. OSCCON1 8.6.2. OSCCON2 8.6.3. OSCCON3 8.6.4. OSCSTAT 8.6.5. OSCEN 8.6.6. OSCTUNE 8.6.7. OSCFRQ 9. REFCLK - Reference Clock Output Module 9.1. Clock Source 9.1.1. Clock Synchronization 9.2. Programmable Clock Divider 9.3. Selectable Duty Cycle 9.4. Operation in Sleep Mode 9.5. Register Summary: Reference CLK 9.6. Register Definitions: Reference Clock 9.6.1. CLKRCON 9.6.2. CLKRCLK 10. Resets 10.1. Power-on Reset (POR) 10.2. Brown-out Reset (BOR) 10.2.1. BOR is Always ON 10.2.2. BOR is OFF in Sleep 10.2.3. BOR Controlled by Software 10.2.4. BOR is Always OFF 10.3. Low-Power Brown-out Reset (LPBOR) 10.3.1. Enabling LPBOR 10.3.2. LPBOR Module Output 10.4. MCLR Reset 10.4.1. MCLR Enabled 10.4.2. MCLR Disabled 10.5. Windowed Watchdog Timer (WWDT) Reset 10.6. RESET Instruction 10.7. Stack Overflow/Underflow Reset 10.8. Programming Mode Exit 10.9. Power-up Timer (PWRT) 10.10. Start-up Sequence 10.11. Memory Execution Violation 10.12. Determining the Cause of a Reset 10.13. Register Summary - BOR Control and Power Control 10.14. Register Definitions: Power Control 10.14.1. BORCON 10.14.2. PCON0 10.14.3. PCON1 11. WWDT - Windowed Watchdog Timer 11.1. Independent Clock Source 11.2. WWDT Operating Modes 11.3. Time-out Period 11.4. Watchdog Window 11.5. Clearing the WWDT 11.5.1. CLRWDT Considerations (Windowed Mode) 11.6. Operation During Sleep 11.7. Register Summary - WDT Control 11.8. Register Definitions: Windowed Watchdog Timer Control 11.8.1. WDTCON0 11.8.2. WDTCON1 11.8.3. WDTPSL 11.8.4. WDTPSH 11.8.5. WDTTMR 12. Power-Saving Operation Modes 12.1. Doze Mode 12.1.1. Doze Operation 12.1.2. Interrupts During Doze 12.2. Sleep Mode 12.2.1. Wake-up from Sleep 12.2.2. Wake-up Using Interrupts 12.2.3. Low-Power Sleep Mode 12.2.3.1. Sleep Current vs. Wake-up Time 12.2.3.2. Peripheral Usage in Sleep 12.3. Idle Mode 12.3.1. Idle and Interrupts 12.3.2. Idle and WWDT 12.4. Register Summary - Power Savings Control 12.5. Register Definitions: Power Savings Control 12.5.1. VREGCON 12.5.2. CPUDOZE 13. PMD - Peripheral Module Disable 13.1. Disabling a Module 13.2. Enabling a Module 13.3. System Clock Disable 13.4. Register Summary - PMD 13.5. Register Definitions: Peripheral Module Disable 13.5.1. PMD0 13.5.2. PMD1 13.5.3. PMD2 13.5.4. PMD3 13.5.5. PMD4 13.5.6. PMD5 13.5.7. PMD6 13.5.8. PMD7 14. I/O Ports 14.1. PORT Availability 14.2. I/O Ports Description 14.3. I/O Priorities 14.4. PORTx Registers 14.4.1. Data Register 14.4.2. Direction Control 14.4.3. Open-Drain Control 14.4.4. Slew Rate Control 14.4.5. Input Threshold Control 14.4.6. Analog Control 14.4.7. Weak Pull-up Control 14.4.8. PORTx Functions and Output Priorities 14.4.9. MCLR/VPP Pin 14.5. Register Summary - Input/Output 14.6. Register Definitions: Port Control 14.6.1. PORTA 14.6.2. PORTB 14.6.3. PORTC 14.6.4. TRISA 14.6.5. TRISB 14.6.6. TRISC 14.6.7. LATA 14.6.8. LATB 14.6.9. LATC 14.6.10. ANSELA 14.6.11. ANSELB 14.6.12. ANSELC 14.6.13. WPUA 14.6.14. WPUB 14.6.15. WPUC 14.6.16. ODCONA 14.6.17. ODCONB 14.6.18. ODCONC 14.6.19. SLRCONA 14.6.20. SLRCONB 14.6.21. SLRCONC 14.6.22. INLVLA 14.6.23. INLVLB 14.6.24. INLVLC 15. IOC - Interrupt-On-Change 15.1. Enabling the Module 15.2. Individual Pin Configuration 15.3. Interrupt Flags 15.3.1. Clearing Interrupt Flags 15.4. Operation in Sleep 15.5. Register Summary - Interrupt-on-Change 15.6. Register Definitions: Interrupt-on-Change Control 15.6.1. IOCAP 15.6.2. IOCAN 15.6.3. IOCAF 15.6.4. IOCBP 15.6.5. IOCBN 15.6.6. IOCBF 15.6.7. IOCCP 15.6.8. IOCCN 15.6.9. IOCCF 16. PPS - Peripheral Pin Select Module 16.1. PPS Inputs 16.2. PPS Outputs 16.3. Bidirectional Pins 16.4. PPS Lock 16.5. PPS1WAY Bit 16.6. Operation During Sleep 16.7. Effects of a Reset 16.8. Register Summary - PPS 16.9. Register Definitions: PPS Input and Output Selection 16.9.1. PPS Lock Register 16.9.2. Peripheral xxx Input Selection 16.9.3. Pin Rxy Output Source Selection Register 17. CLC - Configurable Logic Cell 17.1. CLC Setup 17.1.1. Data Selection 17.1.2. Data Gating 17.1.3. Logic Function 17.1.4. Output Polarity 17.2. CLC Interrupts 17.3. Output Mirror Copies 17.4. Effects of a Reset 17.5. Operation During Sleep 17.6. CLC Setup Steps 17.7. Register Summary - CLC Control 17.8. Register Definitions: Configurable Logic Cell 17.8.1. CLCDATA 17.8.2. CLCxCON 17.8.3. CLCxPOL 17.8.4. CLCxSEL0 17.8.5. CLCxSEL1 17.8.6. CLCxSEL2 17.8.7. CLCxSEL3 17.8.8. CLCxGLS0 17.8.9. CLCxGLS1 17.8.10. CLCxGLS2 17.8.11. CLCxGLS3 18. TMR0 - Timer0 Module 18.1. Timer0 Operation 18.1.1. 8-bit Mode 18.1.2. 16-Bit Mode 18.2. Clock Selection 18.2.1. Clock Source Selection 18.2.2. Synchronous Mode 18.2.3. Asynchronous Mode 18.2.4. Programmable Prescaler 18.3. Timer0 Output and Interrupt 18.3.1. Programmable Postscaler 18.3.2. Timer0 Output 18.3.3. Timer0 Interrupt 18.3.4. Timer0 Example 18.4. Operation During Sleep 18.5. Register Summary - Timer0 18.6. Register Definitions: Timer0 Control 18.6.1. TMR0L 18.6.2. TMR0H 18.6.3. T0CON0 18.6.4. T0CON1 19. TMR1 - Timer1 Module with Gate Control 19.1. Timer1 Operation 19.2. Clock Source Selection 19.2.1. Internal Clock Source 19.2.2. External Clock Source 19.3. Timer1 Prescaler 19.4. Secondary Oscillator 19.5. Timer1 Operation in Asynchronous Counter Mode 19.5.1. Reading and Writing Timer1 in Asynchronous Counter Mode 19.6. Timer1 16-Bit Read/Write Mode 19.7. Timer1 Gate 19.7.1. Timer1 Gate Enable 19.7.2. Timer1 Gate Source Selection 19.7.3. Timer1 Gate Toggle Mode 19.7.4. Timer1 Gate Single Pulse Mode 19.7.5. Timer1 Gate Value Status 19.7.6. Timer1 Gate Event Interrupt 19.8. Timer1 Interrupt 19.9. Timer1 Operation During Sleep 19.10. CCP Capture/Compare Time Base 19.11. CCP Special Event Trigger 19.12. Peripheral Module Disable 19.13. Register Summary - Timer1 19.14. Register Definitions: Timer1 19.14.1. Timer Register 19.14.2. TxCON 19.14.3. TxGCON 19.14.4. TMRxGATE 19.14.5. TMRxCLK 20. TMR2 - Timer2 Module 20.1. Timer2 Operation 20.1.1. Free-Running Period Mode 20.1.2. One-Shot Mode 20.1.3. Monostable Mode 20.2. Timer2 Output 20.3. External Reset Sources 20.4. Timer2 Interrupt 20.5. PSYNC bit 20.6. CSYNC bit 20.7. Operating Modes 20.8. Operation Examples 20.8.1. Software Gate Mode 20.8.2. Hardware Gate Mode 20.8.3. Edge-Triggered Hardware Limit Mode 20.8.4. Level-Triggered Hardware Limit Mode 20.8.5. Software Start One-Shot Mode 20.8.6. Edge-Triggered One-Shot Mode 20.8.7. Edge-Triggered Hardware Limit One-Shot Mode 20.8.8. Level Reset, Edge-Triggered Hardware Limit One-Shot Modes 20.8.9. Edge-Triggered Monostable Modes 20.8.10. Level-Triggered Hardware Limit One-Shot Modes 20.9. Timer2 Operation During Sleep 20.10. Register Summary - Timer2 20.11. Register Definitions: Timer2 Control 20.11.1. TxTMR 20.11.2. TxPR 20.11.3. TxCON 20.11.4. TxHLT 20.11.5. TxCLKCON 20.11.6. TxRST 21. SMT - Signal Measurement Timer 21.1. SMT Operation 21.1.1. Clock Source Selection 21.1.2. Signal and Window Source Selection 21.1.3. Time Base 21.1.4. Capture Pulse Width and Period Registers 21.1.5. Status Information 21.1.6. Modes of Operation 21.1.6.1. Timer Mode 21.1.6.2. Gated Timer Mode 21.1.6.3. Period and Duty Cycle Measurement Mode 21.1.6.4. High and Low Measurement Mode 21.1.6.5. Windowed Measurement Mode 21.1.6.6. Gated Window Measurement Mode 21.1.6.7. Time of Flight Measurement Mode 21.1.6.8. Capture Mode 21.1.6.9. Counter Mode 21.1.6.10. Gated Counter Mode 21.1.6.11. Windowed Counter Mode 21.1.7. Interrupts 21.1.8. Operation During Sleep 21.2. Register Summary - SMT Control 21.3. Register Definitions: SMT Control 21.3.1. SMTxTMR 21.3.2. SMTxCPR 21.3.3. SMTxCPW 21.3.4. SMTxPR 21.3.5. SMTxCON0 21.3.6. SMTxCON1 21.3.7. SMTxSTAT 21.3.8. SMTxCLK 21.3.9. SMTxSIG 21.3.10. SMTxWIN 22. Capture/Compare/PWM Module 22.1. CCP Module Configuration 22.1.1. CCP Modules and Timer Resources 22.1.2. Open-Drain Output Option 22.2. Capture Mode 22.2.1. Capture Sources 22.2.2. Timer1 Mode Resource 22.2.3. Software Interrupt Mode 22.2.4. CCP Prescaler 22.2.5. Capture During Sleep 22.3. Compare Mode 22.3.1. CCPx Pin Configuration 22.3.2. Timer1 Mode Resource 22.3.3. Auto-Conversion Trigger 22.3.4. Compare During Sleep 22.4. PWM Overview 22.4.1. Standard PWM Operation 22.4.2. Setup for PWM Operation 22.4.3. Timer2 Timer Resource 22.4.4. PWM Period 22.4.5. PWM Duty Cycle 22.4.6. PWM Resolution 22.4.7. Operation in Sleep Mode 22.4.8. Changes in System Clock Frequency 22.4.9. Effects of Reset 22.5. Register Summary - CCP Control 22.6. Register Definitions: CCP Control 22.6.1. CCPxCON 22.6.2. CCPxCAP 22.6.3. CCPRx 23. CCP/PWM Timer Resource Selection 23.1. Register Summary - Timer Selection Registers for CCP/PWM 23.2. Register Definitions: CCP/PWM Timer Selection 23.2.1. CCPTMRS0 23.2.2. CCPTMRS1 24. PWM - Pulse-Width Modulation 24.1. Fundamental Operation 24.2. PWM Output Polarity 24.3. PWM Period 24.4. PWM Duty Cycle 24.5. PWM Resolution 24.6. Operation in Sleep Mode 24.7. Changes in System Clock Frequency 24.8. Effects of Reset 24.9. Setup for PWM Operation using PWMx Output Pins 24.9.1. PWMx Pin Configuration 24.10. Setup for PWM Operation to Other Device Peripherals 24.11. Register Summary - Registers Associated with PWM 24.12. Register Definitions: PWM Control 24.12.1. PWMxDC 24.12.2. PWMxCON 25. CWG - Complementary Waveform Generator 25.1. Fundamental Operation 25.2. Operating Modes 25.2.1. Half-Bridge Mode 25.2.2. Push-Pull Mode 25.2.3. Full-Bridge Modes 25.2.3.1. Direction Change in Full-Bridge Mode 25.2.3.2. Dead-Band Delay in Full-Bridge Mode 25.2.4. Steering Modes 25.2.4.1. Synchronous Steering Mode 25.2.4.2. Asynchronous Steering Mode 25.3. Start-up Considerations 25.4. Clock Source 25.5. Selectable Input Sources 25.6. Output Control 25.6.1. CWG Outputs 25.6.2. Polarity Control 25.7. Dead-Band Control 25.7.1. Dead-Band Functionality in Half-Bridge mode 25.7.2. Dead-Band Functionality in Full-Bridge mode 25.8. Rising Edge and Reverse Dead Band 25.9. Falling Edge and Forward Dead Band 25.10. Dead-Band Jitter 25.11. Auto-Shutdown 25.11.1. Shutdown 25.11.1.1. Software Generated Shutdown 25.11.1.2. External Input Source 25.11.1.3. Pin Override Levels 25.11.1.4. Auto-Shutdown Interrupts 25.11.2. Auto-Shutdown Restart 25.11.2.1. Software-Controlled Restart 25.11.2.2. Auto-Restart 25.12. Operation During Sleep 25.13. Configuring the CWG 25.14. Register Summary - CWG Control 25.15. Register Definitions: CWG Control 25.15.1. CWGxCLK 25.15.2. CWGxISM 25.15.3. CWGxDBR 25.15.4. CWGxDBF 25.15.5. CWGxCON0 25.15.6. CWGxCON1 25.15.7. CWGxAS0 25.15.8. CWGxAS1 25.15.9. CWGxSTR 26. NCO - Numerically Controlled Oscillator 26.1. NCO Operation 26.1.1. NCO Clock Sources 26.1.2. Accumulator 26.1.3. Adder 26.1.4. Increment Registers 26.2. Fixed Duty Cycle Mode 26.3. Pulse Frequency Mode 26.3.1. Output Pulse Width Control 26.4. Output Polarity Control 26.5. Interrupts 26.6. Effects of a Reset 26.7. Operation in Sleep 26.8. Register Summary - NCO 26.9. Register Definitions: NCO 26.9.1. NCOxACC 26.9.2. NCOxINC 26.9.3. NCOxCON 26.9.4. NCOxCLK 27. DSM - Data Signal Modulator Module 27.1. DSM Operation 27.2. Modulator Signal Sources 27.3. Carrier Signal Sources 27.4. Carrier Synchronization 27.5. Carrier Source Polarity Select 27.6. Programmable Modulator Data 27.7. Modulated Output Polarity 27.8. Operation in Sleep Mode 27.9. Effects of a Reset 27.10. Peripheral Module Disable 27.11. Register Summary - DSM 27.12. Register Definitions: Modulation Control 27.12.1. MDxCON0 27.12.2. MDxCON1 27.12.3. MDxSRC 27.12.4. MDxCARL 27.12.5. MDxCARH 28. EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter 28.1. EUSART Asynchronous Mode 28.1.1. EUSART Asynchronous Transmitter 28.1.1.1. Enabling the Transmitter 28.1.1.2. Transmitting Data 28.1.1.3. Transmit Data Polarity 28.1.1.4. Transmit Interrupt Flag 28.1.1.5. TSR Status 28.1.1.6. Transmitting 9-Bit Characters 28.1.1.7. Asynchronous Transmission Setup 28.1.2. EUSART Asynchronous Receiver 28.1.2.1. Enabling the Receiver 28.1.2.2. Receiving Data 28.1.2.3. Receive Interrupts 28.1.2.4. Receive Framing Error 28.1.2.5. Receive Overrun Error 28.1.2.6. Receiving 9-Bit Characters 28.1.2.7. Address Detection 28.1.2.8. Asynchronous Reception Setup 28.1.2.9. 9-Bit Address Detection Mode Setup 28.1.3. Clock Accuracy with Asynchronous Operation 28.2. EUSART Baud Rate Generator (BRG) 28.2.1. Auto-Baud Detect 28.2.2. Auto-Baud Overflow 28.2.3. Auto-Wake-up on Break 28.2.3.1. Special Considerations 28.2.4. Break Character Sequence 28.2.4.1. Break and Sync Transmit Sequence 28.2.5. Receiving a Break Character 28.3. EUSART Synchronous Mode 28.3.1. Synchronous Master Mode 28.3.1.1. Master Clock 28.3.1.2. Clock Polarity 28.3.1.3. Synchronous Master Transmission 28.3.1.4. Synchronous Master Transmission Setup 28.3.1.5. Synchronous Master Reception 28.3.1.6. Receive Overrun Error 28.3.1.7. Receiving 9-Bit Characters 28.3.1.8. Synchronous Master Reception Setup 28.3.2. Synchronous Slave Mode 28.3.2.1. Slave Clock 28.3.2.2. EUSART Synchronous Slave Transmit 28.3.2.3. Synchronous Slave Transmission Setup 28.3.2.4. EUSART Synchronous Slave Reception 28.3.2.5. Synchronous Slave Reception Setup: 28.4. EUSART Operation During Sleep 28.4.1. Synchronous Receive During Sleep 28.4.2. Synchronous Transmit During Sleep 28.5. Register Summary - EUSART 28.6. Register Definitions: EUSART Control 28.6.1. RCxREG 28.6.2. TXxREG 28.6.3. SPxBRG 28.6.4. RCxSTA 28.6.5. TXxSTA 28.6.6. BAUDxCON 29. MSSP - Master Synchronous Serial Port Module 29.1. SPI Mode Overview 29.1.1. SPI Mode Registers 29.2. SPI Mode Operation 29.2.1. SPI Master Mode 29.2.2. SPI Slave Mode 29.2.3. Daisy-Chain Configuration 29.2.4. Slave Select Synchronization 29.2.5. SPI Operation in Sleep Mode 29.3. I2C Mode Overview 29.3.1. Register Definitions: I2C Mode 29.4. I2C Mode Operation 29.4.1. Clock Stretching 29.4.2. Arbitration 29.4.3. Byte Format 29.4.4. Definition of I2C Terminology 29.4.5. SDA and SCL Pins 29.4.6. SDA Hold Time 29.4.7. Start Condition 29.4.8. Stop Condition 29.4.9. Restart Condition 29.4.10. Start/Stop Condition Interrupt Masking 29.4.11. Acknowledge Sequence 29.5. I2C Slave Mode Operation 29.5.1. Slave Mode Addresses 29.5.1.1. I2C Slave 7-bit Addressing Mode 29.5.1.2. I2C Slave 10-bit Addressing Mode 29.5.2. Slave Reception 29.5.2.1. 7-bit Addressing Reception 29.5.2.2. 7-bit Reception with AHEN and DHEN 29.5.3. Slave Transmission 29.5.3.1. Slave Mode Bus Collision 29.5.3.2. 7-bit Transmission 29.5.3.3. 7-bit Transmission with Address Hold Enabled 29.5.4. Slave Mode 10-bit Address Reception 29.5.5. 10-bit Addressing with Address or Data Hold 29.5.6. Clock Stretching 29.5.6.1. Normal Clock Stretching 29.5.6.2. 10-bit Addressing Mode 29.5.6.3. Byte NACKing 29.5.7. Clock Synchronization and the CKP bit 29.5.8. General Call Address Support 29.5.9. SSP Mask Register 29.6. I2C Master Mode 29.6.1. I2C Master Mode Operation 29.6.2. Clock Arbitration 29.6.3. WCOL Status Flag 29.6.4. I2C Master Mode Start Condition Timing 29.6.5. I2C Master Mode Repeated Start Condition Timing 29.6.6. I2C Master Mode Transmission 29.6.6.1. BF Status Flag 29.6.6.2. WCOL Status Flag 29.6.6.3. ACKSTAT Status Flag 29.6.6.4. Typical Transmit Sequence: 29.6.7. I2C Master Mode Reception 29.6.7.1. BF Status Flag 29.6.7.2. SSPOV Status Flag 29.6.7.3. WCOL Status Flag 29.6.7.4. Typical Receive Sequence: 29.6.8. Acknowledge Sequence Timing 29.6.8.1. Acknowledge Write Collision 29.6.9. Stop Condition Timing 29.6.9.1. Write Collision on Stop 29.6.10. Sleep Operation 29.6.11. Effects of a Reset 29.6.12. Multi-Master Mode 29.6.13. Multi-Master Communication, Bus Collision and Bus Arbitration 29.6.13.1. Bus Collision During a Start Condition 29.6.13.2. Bus Collision During a Repeated Start Condition 29.6.13.3. Bus Collision During a Stop Condition 29.7. Baud Rate Generator 29.8. Register Summary: MSSP Control 29.9. Register Definitions: MSSP Control 29.9.1. SSPxBUF 29.9.2. SSPxADD 29.9.3. SSPxMSK 29.9.4. SSPxSTAT 29.9.5. SSPxCON1 29.9.6. SSPxCON2 29.9.7. SSPxCON3 30. FVR - Fixed Voltage Reference 30.1. Independent Gain Amplifiers 30.2. FVR Stabilization Period 30.3. Register Summary - FVR 30.4. Register Definitions: FVR Control 30.4.1. FVRCON 31. Temperature Indicator Module 31.1. Module Operation 31.2. Minimum Operating VDD 31.3. Temperature Indicator Range 31.4. Estimation of Temperature 31.4.1. Calibration 31.4.1.1. Higher-Order Calibration 31.4.2. Temperature Resolution 31.5. ADC Acquisition Time 32. ADC2 - Analog-to-Digital Converter 32.1. ADC Configuration 32.1.1. Port Configuration 32.1.2. Channel Selection 32.1.3. ADC Voltage Reference 32.1.4. Conversion Clock 32.1.5. Interrupts 32.1.6. Result Formatting 32.2. ADC Operation 32.2.1. Starting a Conversion 32.2.2. Completion of a Conversion 32.2.3. Terminating a Conversion 32.2.4. ADC Operation During Sleep 32.2.5. External Trigger During Sleep 32.2.6. Auto-Conversion Trigger 32.2.7. ADC Conversion Procedure (Basic Mode) 32.3. ADC Acquisition Requirements 32.4. ADC Charge Pump 32.5. Capacitive Voltage Divider (CVD) Features 32.5.1. CVD Operation 32.5.2. Precharge Control 32.5.3. Acquisition Control for CVD 32.5.4. Guard Ring Outputs 32.5.5. Additional Sample and Hold Capacitance 32.6. Computation Operation 32.6.1. Digital Filter/Average 32.6.2. Basic Mode 32.6.3. Accumulate Mode 32.6.4. Average Mode 32.6.5. Burst Average Mode 32.6.6. Low-pass Filter Mode 32.6.7. Threshold Comparison 32.6.8. Continuous Sampling Mode 32.6.9. Double Sample Conversion 32.7. Register Summary - ADC Control 32.8. Register Definitions: ADC Control 32.8.1. ADLTH 32.8.2. ADUTH 32.8.3. ADERR 32.8.4. ADSTPT 32.8.5. ADFLTR 32.8.6. ADACC 32.8.7. ADCNT 32.8.8. ADRPT 32.8.9. ADPREV 32.8.10. ADRES 32.8.11. ADPCH 32.8.12. ADACQ 32.8.13. ADCAP 32.8.14. ADPRE 32.8.15. ADCON0 32.8.16. ADCON1 32.8.17. ADCON2 32.8.18. ADCON3 32.8.19. ADSTAT 32.8.20. ADREF 32.8.21. ADACT 32.8.22. ADCLK 32.8.23. ADCPCON0 33. DAC - 5-Bit Digital-to-Analog Converter 33.1. Output Voltage Selection 33.2. Ratiometric Output Level 33.3. DAC Voltage Reference Output 33.4. Operation During Sleep 33.5. Effects of a Reset 33.6. Register Summary - DAC Control 33.7. Register Definitions: DAC Control 33.7.1. DAC1CON0 33.7.2. DAC1CON1 34. CMP - Comparator Module 34.1. Comparator Overview 34.2. Comparator Control 34.2.1. Comparator Enable 34.2.2. Comparator Output 34.2.3. Comparator Output Polarity 34.3. Comparator Hysteresis 34.4. Operation With Timer1 Gate 34.4.1. Comparator Output Synchronization 34.5. Comparator Interrupt 34.6. Comparator Positive Input Selection 34.7. Comparator Negative Input Selection 34.8. Comparator Response Time 34.9. Analog Input Connection Considerations 34.10. CWG1 Auto-Shutdown Source 34.11. ADC Auto-Trigger Source 34.12. Even Numbered Timers Reset 34.13. Operation in Sleep Mode 34.14. Register Summary - Comparator 34.15. Register Definitions: Comparator Control 34.15.1. CMOUT 34.15.2. CMxCON0 34.15.3. CMxCON1 34.15.4. CMxNCH 34.15.5. CMxPCH 35. ZCD - Zero-Cross Detection Module 35.1. External Resistor Selection 35.2. ZCD Logic Output 35.3. ZCD Logic Polarity 35.4. ZCD Interrupts 35.5. Correction for ZCPINV Offset 35.5.1. Correction by AC Coupling 35.5.2. Correction By Offset Current 35.6. Handling VPEAK Variations 35.7. Operation During Sleep 35.8. Effects of a Reset 35.9. Disabling the ZCD Module 35.10. Register Summary: ZCD Control 35.11. Register Definitions: ZCD Control 35.11.1. ZCDCON 36. Register Summary 37. Instruction Set Summary 37.1. Read-Modify-Write Operations 37.2. Standard Instruction Set 37.2.1. Standard Instruction Set 38. ICSP™ - In-Circuit Serial Programming™ 38.1. High-Voltage Programming Entry Mode 38.2. Low-Voltage Programming Entry Mode 38.3. Common Programming Interfaces 39. Development Support 39.1. MPLAB X Integrated Development Environment Software 39.2. MPLAB XC Compilers 39.3. MPASM Assembler 39.4. MPLINK Object Linker/MPLIB Object Librarian 39.5. MPLAB Assembler, Linker and Librarian for Various Device Families 39.6. MPLAB X SIM Software Simulator 39.7. MPLAB REAL ICE In-Circuit Emulator System 39.8. MPLAB ICD 3 In-Circuit Debugger System 39.9. PICkit 3 In-Circuit Debugger/Programmer 39.10. MPLAB PM3 Device Programmer 39.11. Demonstration/Development Boards, Evaluation Kits, and Starter Kits 39.12. Third-Party Development Tools 40. Electrical Specifications 40.1. Absolute Maximum Ratings(†) 40.2. Standard Operating Conditions 40.3. DC Characteristics 40.3.1. Supply Voltage 40.3.2. Supply Current (IDD)(1,2,4) 40.3.3. Power-Down Current (IPD)(1,2) 40.3.4. I/O Ports 40.3.5. Memory Programming Specifications 40.3.6. Thermal Characteristics 40.4. AC Characteristics 40.4.1. External Clock/Oscillator Timing Requirements 40.4.2. Internal Oscillator Parameters(1) 40.4.3. PLL Specifications 40.4.4. I/O and CLKOUT Timing Specifications 40.4.5. Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications 40.4.6. Temperature Indicator Requirements 40.4.7. Analog-to-Digital Converter (ADC) Accuracy Specifications(1,2) 40.4.8. Analog-to-Digital Converter (ADC) Conversion Timing Specifications 40.4.9. Comparator Specifications 40.4.10. 5-Bit DAC Specifications 40.4.11. Fixed Voltage Reference (FVR) Specifications 40.4.12. Zero-Cross Detect (ZCD) Specifications 40.4.13. Timer0 and Timer1 External Clock Requirements 40.4.14. Capture/Compare/PWM Requirements (CCP) 40.4.15. Configurable Logic Cell (CLC) Characteristics 40.4.16. EUSART Synchronous Transmission Requirements 40.4.17. EUSART Synchronous Receive Requirements 40.4.18. SPI Mode Requirements 40.4.19. I2C Bus Start/Stop Bits Requirements 40.4.20. I2C Bus Data Requirements 41. DC and AC Characteristics Graphs and Tables 41.1. Graphs 42. Packaging Information 42.1. Package Details 43. Revision History The Microchip Website Product Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service
