Product Brief PIC18F27Q10 (Microchip) - 9

PIC18F2X/4XQ10 ...continued 28-Pin SPDIP, 28-Pin Pull- I/O(2) A/D Reference Comparator Timers CCP CWG ZCD Interrupt EUSART DSM MSSP Basic SOIC, VQFN up SSOP
VDD(5) 20 17 — — — — — — — — — — — — VDD VSS 8 5 — — — — — — — — — — — — VSS OUT(2) — — ADGRDA — C1OUT TMR0 CCP1 CWG1A — — TX1/CK1(3) DSM SDO1 — — ADGRDB C2OUT CCP2 CWG1B DT1(3) SCK1 PWM3 CWG1C PWM4 CWG1D
Note: 
1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the peripheral input selection table for details on which port pins may be used for this signal. 2. All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the peripheral output selection table. 3. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. 4. These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds. 5. A 0.1 uF bypass capacitor to VSS is required on the VDD pin.
Table 3.  40/44-Pin Allocation Table 40- 44-Pin Pull- I/O(2) 40-Pin Pin A/D Reference Comparator Timers CCP CWG ZCD Interrupt EUSART DSM MSSP Basic PDIP TQFP up QFN
RA0 2 17 19 ANA0 — C1INO- — — — — IOCA0 — — — Y — C2IN0- RA1 3 18 20 ANA1 — C1IN1- — — — — IOCA1 — — — Y — C2IN1- RA2 4 19 21 ANA2 DAC1OUT1 C1IN0+ — — — — IOCA2 — — — Y — VREF- C2IN0+ (DAC5) VREF- (ADC) RA3 5 20 22 ANA3 VREF+ C1IN1+ — — — — IOCA3 — MDCARL(1) — Y — (DAC5) VREF+ (ADC) RA4 6 21 23 ANA4 — — T0CKI(1) — — — IOCA4 — MDCARH(1) — Y — RA5 7 22 24 ANA5 — — — — — — IOCA5 — MDSRC(1) SS1(1) Y — RA6 14 29 31 ANA6 — — — — — — IOCA6 — — — Y CLKOUT OSC2 RA7 13 28 30 ANA7 — — — — — — IOCA7 — — — Y OSC1 CLKIN RB0 33 8 8 ANB0 — C2IN1+ — — CWG1(1) ZCDIN IOCB0 — — SS2(1) Y — INT0(1) RB1 34 9 9 ANB1 — C1IN3- — — — — IOCB1 — — SCK2(1) Y — C2IN3- INT1(1) SCL2(3,4) RB2 35 10 10 ANB2 — — — — — — IOCB2 — — SDI2(1) Y — INT2(1) SDA2(3,4) RB3 36 11 11 ANB3 — C1IN2- — — — — IOCB3 — — — Y — C2IN2- © 2019 Microchip Technology Inc.
Product Brief
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