Data Brief AK8464 (Asahi Kasei Microdevices) - 6

Product Brief
[AK8464]
4.3. Block Functions
 REF(Reference): Reference Voltage Generation Circuit This block generates sensoer referenve voltage, (VCLP), ADC reference voltage and internal reference current.  CDS/Clamp/SH: Sensor Interface Circuit This circuit samples pixel signal level of sensor ouput. Three modes are available for sampling: CDS mode, clamp mode and DC direct mode.  DAC: D/A Converter for Adding Offset Offset voltage that is added to the sampling signal at sensor interface is generated in this block. DAC setting range is more than ±381mV (min.) and the resolution is 25.4mV/step. Offset voltage can be set independently for each channel by register settings. Automatic offset compensation sequence is also available.  PGA: Gain Adjustment Circuit It is a programmable analog gain amplifier that can adjust signal amplitude for each channel. The gain setting range is 0dB or 6dB (typ.). Gain setting can be applied independently for each channel by register setting. Automatic gain adjustment sequence is also available.  ADC: A/D Converter It is a 14bit 35MSPS A/D converter that converts pixel signal to digital data after gain adjustment and offset compensation.  Black_cal: Black Level Correction Circuit Sampled black level during <OBP> period is automatically calibrated to the setting black level ([BLKLVL] register). This function is for CCD sonsors. Offset level should be set manually with CIS sensors.  Gain_cal: Gain Correction Circuit Sampled white level (peak value) during pixel detection period (<AGC_EN>) is automatically calibrated to the setting code ([WLVL]) by PGA and D-gain. This function is for CCD sensors. Gain level should be set manually for CIS sensors.  Serializer This block converts parallel data of ADC each channel output into serial data.  LVDS: LVDS Interface Circuit This block is output buffer that outputs ADC output in LVDS level. The output data consists of 5 data pairs and 1 clock pair. Rev.1.00E 2019/6 - 6 -