Datasheet STM32WLE5J8, STM32WLE5JB, STM32WLE5JC (STMicroelectronics) - 7

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STM32WLE5J8/JB/JC List of tables List of tables
Table 1. Device summary . 2 Table 2. Main features and peripheral counts . 11 Table 3. Access status versus RDP level and execution mode . 15 Table 4. Sub-GHz radio transmit high output power. 19 Table 5. FSK mode intermediate frequencies . 21 Table 6. LoRa mode intermediate frequencies. 21 Table 7. Functionalities depending on system operating mode . 28 Table 8. Low-power mode summary . 30 Table 9. MCU and sub-GHz radio operating modes. 31 Table 10. Peripherals interconnect matrix . 32 Table 11. DMA1 and DMA2 implementation . 36 Table 12. Temperature sensor calibration values. 38 Table 13. Internal voltage reference calibration values . 38 Table 14. Timer features. 40 Table 15. I2C implementation . 43 Table 16. USART/LPUART features . 45 Table 17. SPI and SPI/I2S implementation . 46 Table 18. Legend/abbreviations used in the pinout table . 47 Table 19. STM32WLE5J8/JB/JC pin definition . 48 Table 20. Alternate functions . 53 Table 21. Voltage characteristics . 59 Table 22. Current characteristics . 60 Table 23. Thermal characteristics. 60 Table 24. Main performances at VDD = 3 V . 61 Table 25. General operating conditions . 61 Table 26. Sub-GHz radio power consumption . 63 Table 27. Sub-GHz radio power consumption in transmit mode (SMPS ON) . 64 Table 28. Sub-GHz radio general specifications . 65 Table 29. Sub-GHz radio receive mode specifications . 66 Table 30. Sub-GHz radio transmit mode specifications . 67 Table 31. Sub-GHz radio power management specifications. 68 Table 32. Operating conditions at power-up/power-down . 69 Table 33. Embedded reset and power-control block characteristics . 69 Table 34. Embedded internal voltage reference. 71 Table 35. Current consumption in Run and LPRun modes, CoreMark code with data running from Flash memory, ART enable (cache ON, prefetch OFF) . 73 Table 36. Current consumption in Run and LPRun modes, CoreMark code with data running from SRAM1 . 74 Table 37. Typical current consumption in Run and LPRun modes, with different codes running from Flash memory, ART enable (cache ON, prefetch OFF) . 75 Table 38. Typical current consumption in Run and LPRun modes, with different codes running from SRAM1 . 77 Table 39. Current consumption in Sleep and LPSleep modes, Flash memory ON . 79 Table 40. Current consumption in LPSleep mode, Flash memory in power-down . 80 Table 41. Current consumption in Stop 2 mode . 80 Table 42. Current consumption in Stop 1 mode . 81 Table 43. Current consumption in Stop 0 mode . 81 Table 44. Current consumption in Standby mode . 82 DS13105 Rev 2 7/135 8 Document Outline Table 1. Device summary 1 Introduction 2 Description Table 2. Main features and peripheral counts Figure 1. STM32WLE5J8/JB/JC block diagram 3 Functional overview 3.1 Architecture 3.2 Arm Cortex-M4 core 3.3 Adaptive real-time memory accelerator (ART Accelerator) 3.4 Memory protection unit (MPU) 3.5 Memories 3.5.1 Embedded Flash memory Table 3. Access status versus RDP level and execution mode 3.5.2 Embedded SRAM 3.6 Security memory management 3.7 Boot modes 3.8 Sub-GHz radio 3.8.1 Introduction 3.8.2 General description Figure 2. sub-GHz radio system block diagram 3.8.3 Transmitter Transmitter high output power Figure 3. High output power PA Table 4. Sub-GHz radio transmit high output power Transmitter low output power Figure 4. Low output power PA 3.8.4 Receiver 3.8.5 RF-PLL 3.8.6 Intermediate frequencies Table 5. FSK mode intermediate frequencies Table 6. LoRa mode intermediate frequencies 3.9 Power supply management 3.9.1 Power supply schemes Figure 5. Power supply overview Figure 6. Supply configurations 3.9.2 Power supply supervisor 3.9.3 Linear voltage regulator 3.9.4 VBAT operation 3.10 Low-power modes Table 7. Functionalities depending on system operating mode Table 8. Low-power mode summary Relation between MCU and sub-GHz radio operating modes Table 9. MCU and sub-GHz radio operating modes 3.10.1 Reset mode 3.11 Peripheral interconnect matrix Table 10. Peripherals interconnect matrix 3.12 Reset and clock controller (RCC) Figure 7. Clock tree 3.13 General-purpose inputs/outputs (GPIOs) 3.14 Directly memory access controller (DMA) Table 11. DMA1 and DMA2 implementation 3.15 Interrupts and events 3.15.1 Nested vectored interrupt controller (NVIC) 3.15.2 Extended interrupt/event controller (EXTI) 3.16 Analog-to-digital converter (ADC) 3.16.1 Temperature sensor Table 12. Temperature sensor calibration values 3.16.2 Internal voltage reference (VREFINT) Table 13. Internal voltage reference calibration values 3.16.3 VBAT battery voltage monitoring 3.17 Voltage reference buffer (VREFBUF) 3.18 Digital-to-analog converter (DAC) 3.19 Comparator (COMP) 3.20 True random number generator (RNG) 3.21 Advanced encryption standard hardware accelerator (AES) 3.22 Public key accelerator (PKA) 3.23 Timer and watchdog Table 14. Timer features 3.23.1 Advanced-control timer (TIM1) 3.23.2 General-purpose timers (TIM2, TIM16, TIM17) 3.23.3 Low-power timers (LPTIM1, LPTIM2 and LPTIM3) 3.23.4 Independent watchdog (IWDG) 3.23.5 System window watchdog (WWDG) 3.23.6 SysTick timer 3.24 Real-time clock (RTC), tamper and backup registers 3.25 Inter-integrated circuit interface (I2C) Table 15. I2C implementation 3.26 Universal synchronous/asynchronous receiver transmitter (USART/UART) 3.27 Low-power universal asynchronous receiver transmitter (LPUART) Table 16. USART/LPUART features 3.28 Serial peripheral interface (SPI)/integrated-interchip sound interface (I2S) Table 17. SPI and SPI/I2S implementation 3.29 Development support Serial-wire JTAG debug port (SWJ-DP) 4 Pinouts, pin description and alternate functions Figure 8. UFBGA73 pinout Table 18. Legend/abbreviations used in the pinout table Table 19. STM32WLE5J8/JB/JC pin definition Table 20. Alternate functions 5 Electrical characteristics 5.1 Parameter conditions 5.1.1 Minimum and maximum values 5.1.2 Typical values 5.1.3 Typical curves 5.1.4 Loading capacitor 5.1.5 Pin input voltage Figure 9. Pin loading conditions Figure 10. Pin input voltage 5.1.6 Power supply scheme Figure 11. Power supply scheme 5.1.7 Current consumption measurement Figure 12. Current consumption measurement scheme 5.2 Absolute maximum ratings Table 21. Voltage characteristics Table 22. Current characteristics Table 23. Thermal characteristics 5.3 Operating conditions 5.3.1 Main performances Table 24. Main performances at VDD = 3 V 5.3.2 General operating conditions Table 25. General operating conditions 5.3.3 Sub-GHz radio characteristics Table 26. Sub-GHz radio power consumption Table 27. Sub-GHz radio power consumption in transmit mode (SMPS ON) Table 28. Sub-GHz radio general specifications Table 29. Sub-GHz radio receive mode specifications Table 30. Sub-GHz radio transmit mode specifications Table 31. Sub-GHz radio power management specifications 5.3.4 Operating conditions at power-up/power-down Table 32. Operating conditions at power-up/power-down 5.3.5 Embedded reset and power-control block characteristics Table 33. Embedded reset and power-control block characteristics 5.3.6 Embedded voltage reference Table 34. Embedded internal voltage reference Figure 13. VREFINT versus temperature 5.3.7 Supply current characteristics Typical and maximum current consumption Table 35. Current consumption in Run and LPRun modes, CoreMark code with data running from Flash memory, ART enable (cache ON, prefetch OFF) Table 36. Current consumption in Run and LPRun modes, CoreMark code with data running from SRAM1 Table 37. Typical current consumption in Run and LPRun modes, with different codes running from Flash memory, ART enable (cache ON, prefetch OFF) Table 38. Typical current consumption in Run and LPRun modes, with different codes running from SRAM1 Table 39. Current consumption in Sleep and LPSleep modes, Flash memory ON Table 40. Current consumption in LPSleep mode, Flash memory in power-down Table 41. Current consumption in Stop 2 mode Table 42. Current consumption in Stop 1 mode Table 43. Current consumption in Stop 0 mode Table 44. Current consumption in Standby mode Table 45. Current consumption in Shutdown mode Table 46. Current consumption in VBAT mode Table 47. Current under Reset condition I/O system current consumption On-chip peripheral current consumption Table 48. Peripheral current consumption 5.3.8 Wakeup time from low-power modes and voltage scaling transition times Table 49. Low-power mode wakeup timings Table 50. Regulator modes transition times 5.3.9 External clock source characteristics High-speed external user clock generated from an external source Crystal oscillator Table 51. HSE32 crystal requirements Table 52. HSE32 oscillator characteristics TCXO Table 53. HSE32 TCXO characteristics Low-speed external user clock generated from an external source Table 54. Low-speed external user clock characteristics Figure 14. Typical application with a 32.768 kHz crystal Figure 15. Low-speed external clock source AC timing diagram Table 55. Low-speed external user clock characteristics – Bypass mode 5.3.10 Internal clock source characteristics High-speed internal (HSI16) RC oscillator Table 56. HSI16 oscillator characteristics Figure 16. HSI16 frequency versus temperature Multi-speed internal (MSI) RC oscillator Table 57. MSI oscillator characteristics Figure 17. Typical current consumption vs. MSI frequency Low-speed internal (LSI) RC oscillator Table 58. LSI1 oscillator characteristics Table 59. LSI2 oscillator characteristics 5.3.11 PLL characteristics Table 60. PLL characteristics 5.3.12 Flash memory characteristics Table 61. Flash memory characteristics Table 62. Flash memory endurance and data retention 5.3.13 EMC characteristics Functional EMS (electromagnetic susceptibility) Table 63. EMS characteristics Designing hardened software to avoid noise problems Electromagnetic interference (EMI) Table 64. EMI characteristics 5.3.14 Electrical sensitivity characteristics Electrostatic discharge (ESD) Table 65. ESD absolute maximum ratings Static latch-up Table 66. Electrical sensitivities 5.3.15 I/O current injection characteristics Functional susceptibility to I/O current injection Table 67. I/O current injection susceptibility 5.3.16 I/O port characteristics General input/output characteristics Table 68. I/O static characteristics Figure 18. I/O input characteristics - VIL and VIH on all I/Os except BOOT0 Output driving current Output voltage levels Table 69. Output voltage characteristics Input/output AC characteristics Table 70. I/O AC characteristics 5.3.17 NRST pin characteristics Table 71. NRST pin characteristics Figure 19. Recommended NRST pin protection 5.3.18 Analog switches booster Table 72. Analog switches booster characteristics 5.3.19 Analog-to-digital converter characteristics Table 73. ADC characteristics Table 74. Maximum ADC RAIN values Table 75. ADC accuracy Figure 20. ADC accuracy characteristics Figure 21. Typical connection diagram using the ADC General PCB design guidelines 5.3.20 Temperature sensor characteristics Table 76. TS characteristics 5.3.21 VBAT monitoring characteristics Table 77. VBAT monitoring characteristics Table 78. VBAT charging characteristics 5.3.22 Voltage reference buffer characteristics Table 79. VREFBUF characteristics 5.3.23 Digital-to-analog converter characteristics Table 80. DAC characteristics Figure 22. 12-bit buffered/non-buffered DAC Table 81. DAC accuracy 5.3.24 Comparator characteristics Table 82. COMP characteristics 5.3.25 Timers characteristics Table 83. TIMx characteristics Table 84. IWDG min/max timeout period at 32 kHz (LSI1) 5.3.26 Communication interfaces characteristics I2C interface characteristics Table 85. Minimum I2CCLK frequency in all I2C modes Table 86. I2C analog filter characteristics USART characteristics Table 87. USART characteristics SPI characteristics Table 88. SPI characteristics Figure 23. SPI timing diagram - Slave mode and CPHA = 0 Figure 24. SPI timing diagram - Slave mode and CPHA = 1 Figure 25. SPI timing diagram - Master mode JTAG/SWD characteristics Table 89. Dynamic JTAG characteristics Table 90. Dynamic SWD characteristics 6 Package information 6.1 UFBGA73 package information Figure 26. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array package outline Table 91. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array mechanical data Figure 27. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array recommended footprint Table 92. UFBGA recommended PCB design rules (0.5 mm pitch BGA) Device marking for UFBGA73 Figure 28. UFBGA73 marking example (package top view) 6.2 Package thermal characteristics Table 93. Package thermal characteristics 7 Ordering information 8 Revision history Table 94. Document revision history