Datasheet LTC3780 (Analog Devices) - 25

LTC3780
APPLICATIONS INFORMATION
• Use immediate vias to connect the components (in- • The output capacitor (–) terminals should be connected cluding the LTC3780’s SGND and PGND pins) to the as close as possible the (–) terminals of the input ground plane. Use several large vias for each power capacitor. component. • Connect the top driver boost capacitor CA closely to the • Use planes for VIN and VOUT to maintain good voltage BOOST1 and SW1 pins. Connect the top driver boost filtering and to keep power losses low. capacitor CB closely to the BOOST2 and SW2 pins. • Flood all unused areas on all layers with copper. Flooding • Connect the input capacitors CIN and output capacitors with copper will reduce the temperature rise of power COUT closely to the power MOSFETs. These capacitors components. Connect the copper areas to any DC net carry the MOSFET AC current in boost and buck mode. (VIN or GND). • Connect VOSENSE pin resistive dividers to the (+) termi- • Segregate the signal and power grounds. All small- nals of COUT and signal ground. A small VOSENSE bypass signal components should return to the SGND pin at capacitor may be connected closely to the LTC3780 one point, which is then tied to the PGND pin close to SGND pin. The R2 connection should not be along the the sources of switch B and switch C. high current or noise paths, such as the input capaci- • Place switch B and switch C as close to the controller as tors. possible, keeping the PGND, BG and SW traces short. • Route SENSE– and SENSE+ leads together with minimum • Keep the high dV/dT SW1, SW2, BOOST1, BOOST2, PC trace spacing. Avoid sense lines pass through noisy TG1 and TG2 nodes away from sensitive small-signal area, such as switch nodes. The filter capacitor between nodes. SENSE+ and SENSE– should be as close as possible to the IC. Ensure accurate current sensing with Kelvin • The path formed by switch A, switch B, D1 and the CIN connections at the SENSE resistor. One layout example capacitor should have short leads and PC trace lengths. is shown in Figure 12. The path formed by switch C, switch D, D2 and the C • Connect the ITH pin compensation network close to the OUT capacitor also should have short leads and PC trace lengths. IC, between ITH and the signal ground pins. The capaci- tor helps to filter the effects of PCB noise and output voltage ripple voltage from the compensation loop. • Connect the INTVCC bypass capacitor, CVCC, close to the IC, between the INTVCC and the power ground pins. This capacitor carries the MOSFET drivers’ current peaks. An additional 1µF ceramic capacitor placed immediately next to the INTVCC and PGND pins can help improve noise performance substantially. Rev G For more information www.analog.com 25 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Block Diagram Operation Applications Information Typical Application Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts