Datasheet ADP5076 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | 2 A/1.2 A DC-to-DC Switching Regulator with Independent Positive and Negative Outputs |
| Pages / Page | 23 / 1 — 2 A/1.2 A DC-to-DC Switching Regulator with. Independent Positive and … |
| Revision | A |
| File Format / Size | PDF / 725 Kb |
| Document Language | English |
2 A/1.2 A DC-to-DC Switching Regulator with. Independent Positive and Negative Outputs. Data Sheet. ADP5076. FEATURES
Model Line for this Datasheet
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2 A/1.2 A DC-to-DC Switching Regulator with Independent Positive and Negative Outputs Data Sheet ADP5076 FEATURES
The ADP5076 includes a fixed internal or resistor programmable soft start timer to prevent inrush current at power-up.
Input supply voltage range: 2.85 V to 5.5 V Generates well regulated, independently resistor
Other key safety features in the ADP5076 include overcurrent
programmable VPOS and VNEG outputs
protection (OCP), overvoltage protection (OVP), thermal
Boost regulator to generate VPOS output
shutdown (TSD), and input undervoltage lockout (UVLO).
Adjustable positive output to 35 V
The ADP5076 is available in a 20-ball wafer level chip scale
Integrated 2.0 A main switch
package (WLCSP) and is rated for a −40°C to +125°C junction
Inverting regulator to generate VNEG output
temperature range.
Adjustable negative output to −30 V Integrated 1.20 A main switch Table 1. Family Models 1.2 MHz or 2.4 MHz switching frequency with optional Boost Inverter external frequency synchronization from 1.0 MHz to Model Switch (A) Switch (A) Package 2.6 MHz
ADP5070 1.0 0.6 20-lead LFCSP (4 mm ×
Resistor programmable soft start timer
4 mm) and 20-lead TSSOP
Slew rate control for lower system noise
ADP5071 2.0 1.2 20-lead LFCSP (4 mm × 4 mm) and 20-lead TSSOP
Individual precision enable and flexible start-up sequence
ADP5072 1.0 0.6 20-ball WLCSP
control for symmetric start, VPOS first, or VNEG first
(1.61 mm × 2.18 mm)
Out of phase operation
ADP5073 N/A1 1.2 16-lead LFCSP (3 mm ×
UVLO, OCP, OVP, and TSD protection
3 mm)
1.61 mm × 2.18 mm, 20-ball WLCSP
ADP5074 N/A1 2.4 16-lead LFCSP (3 mm ×
−40°C to +125°C junction temperature range
3 mm)
APPLICATIONS
ADP5075 N/A1 0.8 12-ball WLCSP (1.61 mm × 2.18 mm)
Bipolar amplifiers, ADCs, DACs, and multiplexers
ADP5076 2.0 1.2 20-ball WLCSP
Charge coupled device (CCD) bias supply
(1.61 mm × 2.18 mm)
Optical module supply
1 N/A means not applicable.
RF power amplifier bias FUNCTIONAL BLOCK DIAGRAM Time of flight module supply VIN GENERAL DESCRIPTION ADP5076
The ADP5076 is a dual, high performance, dc-to-dc regulator that
SS L1 R V C1 POS
generates independently regulated positive and negative rails. The
COMP1 SW1 C D1 C1 SW1
input voltage range of 2.85 V to 5.5 V supports a wide variety of
R EN1 FT1
applications. The integrated main switch in both regulators enables
FB1 RFB1 C
generation of an adjustable positive output voltage up to +35 V and
OUT1 PVIN V
a negative output voltage down to −30 V.
IN PVIN PGND C AVIN IN PGND C
The ADP5076 operates at a pin selected 1.2 MHz or 2.4 MHz
VREF VREF
switching frequency. The ADP5076 can synchronize with an
EN2 RFB2 COUT2
external oscillator from 1.0 MHz to 2.6 MHz to ease noise
RC2 COMP2 FB2
filtering in sensitive applications. Both regulators implement
C R C2 FT2
programmable slew rate control circuitry for the metal-oxide
SYNC SW2 SLEW V
semiconductor field effect transistor (MOSFET) driver stage to
D2 NEG SEQ AGND L2
1 reduce electromagnetic interference (EMI). Flexible start-up 00 2- 40 sequencing is provided with the options of manual enable, 20 simultaneous mode, positive supply first, and negative supply first. Figure 1.
Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PULSE WIDTH MODULATION (PWM) MODE PULSE SKIP MODULATION MODE UVLO OSCILLATOR AND SYNCHRONIZATION INTERNAL REGULATOR PRECISION ENABLING SOFT START SLEW RATE CONTROL CURRENT-LIMIT PROTECTION OVERVOLTAGE PROTECTION THERMAL SHUTDOWN STARTUP SEQUENCE APPLICATIONS INFORMATION COMPONENT SELECTION Feedback Resistors OUTPUT CAPACITORS Input Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator LOOP COMPENSATION Boost Regulator Inverting Regulator COMMON APPLICATIONS LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE
The ADP5076 includes a fixed internal or resistor programmable soft start timer to prevent inrush current at power-up.
Input supply voltage range: 2.85 V to 5.5 V Generates well regulated, independently resistor
Other key safety features in the ADP5076 include overcurrent
programmable VPOS and VNEG outputs
protection (OCP), overvoltage protection (OVP), thermal
Boost regulator to generate VPOS output
shutdown (TSD), and input undervoltage lockout (UVLO).
Adjustable positive output to 35 V
The ADP5076 is available in a 20-ball wafer level chip scale
Integrated 2.0 A main switch
package (WLCSP) and is rated for a −40°C to +125°C junction
Inverting regulator to generate VNEG output
temperature range.
Adjustable negative output to −30 V Integrated 1.20 A main switch Table 1. Family Models 1.2 MHz or 2.4 MHz switching frequency with optional Boost Inverter external frequency synchronization from 1.0 MHz to Model Switch (A) Switch (A) Package 2.6 MHz
ADP5070 1.0 0.6 20-lead LFCSP (4 mm ×
Resistor programmable soft start timer
4 mm) and 20-lead TSSOP
Slew rate control for lower system noise
ADP5071 2.0 1.2 20-lead LFCSP (4 mm × 4 mm) and 20-lead TSSOP
Individual precision enable and flexible start-up sequence
ADP5072 1.0 0.6 20-ball WLCSP
control for symmetric start, VPOS first, or VNEG first
(1.61 mm × 2.18 mm)
Out of phase operation
ADP5073 N/A1 1.2 16-lead LFCSP (3 mm ×
UVLO, OCP, OVP, and TSD protection
3 mm)
1.61 mm × 2.18 mm, 20-ball WLCSP
ADP5074 N/A1 2.4 16-lead LFCSP (3 mm ×
−40°C to +125°C junction temperature range
3 mm)
APPLICATIONS
ADP5075 N/A1 0.8 12-ball WLCSP (1.61 mm × 2.18 mm)
Bipolar amplifiers, ADCs, DACs, and multiplexers
ADP5076 2.0 1.2 20-ball WLCSP
Charge coupled device (CCD) bias supply
(1.61 mm × 2.18 mm)
Optical module supply
1 N/A means not applicable.
RF power amplifier bias FUNCTIONAL BLOCK DIAGRAM Time of flight module supply VIN GENERAL DESCRIPTION ADP5076
The ADP5076 is a dual, high performance, dc-to-dc regulator that
SS L1 R V C1 POS
generates independently regulated positive and negative rails. The
COMP1 SW1 C D1 C1 SW1
input voltage range of 2.85 V to 5.5 V supports a wide variety of
R EN1 FT1
applications. The integrated main switch in both regulators enables
FB1 RFB1 C
generation of an adjustable positive output voltage up to +35 V and
OUT1 PVIN V
a negative output voltage down to −30 V.
IN PVIN PGND C AVIN IN PGND C
The ADP5076 operates at a pin selected 1.2 MHz or 2.4 MHz
VREF VREF
switching frequency. The ADP5076 can synchronize with an
EN2 RFB2 COUT2
external oscillator from 1.0 MHz to 2.6 MHz to ease noise
RC2 COMP2 FB2
filtering in sensitive applications. Both regulators implement
C R C2 FT2
programmable slew rate control circuitry for the metal-oxide
SYNC SW2 SLEW V
semiconductor field effect transistor (MOSFET) driver stage to
D2 NEG SEQ AGND L2
1 reduce electromagnetic interference (EMI). Flexible start-up 00 2- 40 sequencing is provided with the options of manual enable, 20 simultaneous mode, positive supply first, and negative supply first. Figure 1.
Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PULSE WIDTH MODULATION (PWM) MODE PULSE SKIP MODULATION MODE UVLO OSCILLATOR AND SYNCHRONIZATION INTERNAL REGULATOR PRECISION ENABLING SOFT START SLEW RATE CONTROL CURRENT-LIMIT PROTECTION OVERVOLTAGE PROTECTION THERMAL SHUTDOWN STARTUP SEQUENCE APPLICATIONS INFORMATION COMPONENT SELECTION Feedback Resistors OUTPUT CAPACITORS Input Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator LOOP COMPENSATION Boost Regulator Inverting Regulator COMMON APPLICATIONS LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE
