Datasheet STSPIN32F0601, STSPIN32F0602 (STMicroelectronics) - 8

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Electrical data STSPIN32F0601, STSPIN32F0602 3 Electrical data 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings(1) Symbol Parameter Test condition Min. Max. Unit
VCC Power supply voltage -0.3 21 V VPGND Low-side driver ground VCC - 21 VCC + 0.3 V V (2) PS Low-side driver ground -21 21 V VOUT Output voltage VBOOT - 21 VBOOT + 0.3 V VBOOT Bootstrap voltage -0.3 620 V VHVG High-side gate output voltage VOUT - 0.3 VBOOT + 0.3 V VLVG Low-side gate output voltage VPGND - 0.3 VCC + 0.3 V VCIN Comparator input voltage -0.3 20 V VOD Open-drain voltage (OD, FAULT) -0.3 21 V dVOUT/dt Common mode transient Immunity 50 V/ns MCU logic input voltage TTa type(3) -0.3 4 V VIO Logic input voltage FT, FTf type(3) -0.3 VDD + 4(4) V IIO MCU I/O output current (3) -25 25 mA ΣIIO MCU I/O total output current (3) -80 80 mA VDD MCU digital supply voltage (3) -0.3 4 V VDDA MCU analog supply voltage (3) -0.3 4 V Tstg Storage temperature -50 150 °C TJ Junction temperature -40 150 °C PTOT Total power dissipation 4.5 W ESD Human Body Model 2(5) kV 1. Each voltage referred to SGND unless otherwise specified. 2. VPS = VPGND - VSGND 3. For details see Table 15 and 16 in the STM32F031x6x7 datasheet. 4. Valid only if the internal pull-up/pull-down resistors are disabled. If the internal pull-up or pull-down resistor is enabled, the maximum limit is 4 V. 5. Pins 33 to 48 have HBM ESD rating 1C conforming to ANSI/ESDA/JEDEC JS-001-2014. 8/29 DS12981 Rev 3 Document Outline 1 Block diagram Figure 1. STSPIN32F060x SiP block diagram 2 Pin description and connection diagram Figure 2. STSPIN32F060x pin connection (Top view) Table 1. Legend/abbreviations used in the pin description table Table 2. Pin description Table 3. STSPIN32F060x MCU-Driver internal connections 3 Electrical data 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings 3.2 Thermal data Table 5. Thermal data 3.3 Recommended operating conditions Table 6. Recommended operating conditions 4 Electrical characteristics Table 7. Electrical characteristics Figure 3. Propagation delay timing definition Figure 4. Deadtime timing definitions Figure 5. Deadtime and interlocking waveforms definition 5 Device description 5.1 Gate driver 5.1.1 Inputs and outputs Table 8. Inputs truth table (applicable when device is not in UVLO or SmartSD protection) 5.1.2 Deadtime 5.1.3 VCC UVLO protection Figure 6. VCC power ON and UVLO, LVG timing Figure 7. VCC power ON and UVLO, HVG timing 5.1.4 VBO UVLO protection Figure 8. VBO Power-ON and UVLO timing 5.1.5 Comparator and Smart shutdown Figure 9. Smart shutdown timing waveforms 5.2 Microcontroller unit 5.2.1 Memories and boot mode 5.2.2 Power management 5.2.3 High-speed external clock source Figure 10. Typical application with 8 MHz crystal Figure 11. HSE clock source timing diagram 5.3 Advanced-control timer (TIM1) Table 9. TIM1 channel configuration 6 Package information 6.1 TQFP 10x10 64L package information Figure 12. TQFP mechanical data Table 10. TQFP package dimensions 6.2 Suggested land pattern Figure 13. TQFP 10x10 64L suggested land pattern 7 Ordering information Table 11. Order codes 8 Revision history Table 12. Document revision history