Datasheet (Asahi Kasei Microdevices) - 9
| Manufacturer | Asahi Kasei Microdevices |
| Description | LED Driver and Sensor AFE for NDIR Gas Sensing |
| Pages / Page | 34 / 9 — 10.2.2. AC Characteristics |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
10.2.2. AC Characteristics
Model Line for this Datasheet
Text Version of Document
[AK9723AJ]
10.2.2. AC Characteristics
Table 10.4 AC Characteristics (Standard Mode: fSCL ≤ 100kHz) Unless otherwise specified, AVDD = 2.7 ~ 3.6V, Ta = -40 ~ 85ºC Parameter Symbol Min. Typ. Max. Unit SCL clock frequency fSCL - - 100 kHz SCL clock high period tHIGH 4.0 - - µs SCL clock low period tLOW 4.7 - - µs SDA and SCL rise time (*2) tR - - 1.0 µs SDA and SCL fall time (*2) tF - - 0.3 µs Start condition hold time tHD:STA 4.0 - - µs Start condition setup time tSU:STA 4.7 - - µs SDA hold time (vs. SCL falling edge) tHD:DAT 0 - - µs SDA setup time (vs. SCL rising edge) tSU:DAT 250 - - ns Stop condition setup time tSU:STO 4.0 - - µs Bus free time tBUF 4.7 - - µs Note *2. Reference data only, not tested Table 10.5 AC Characteristics (Fast Mode: 100kHz ≤ fSCL ≤ 400kHz) Unless otherwise specified, AVDD = 2.7 ~ 3.6V, Ta = -40 ~ 85ºC Parameter Symbol Min. Typ. Max. Unit SCL clock frequency fSCL - - 400 kHz SCL clock high period tHIGH 0.6 - - µs SCL clock low period tLOW 1.3 - - µs SDA and SCL rise time (*3) tR - - 0.3 µs SDA and SCL fall time (*3) tF - - 0.3 µs Start condition hold time tHD:STA 0.6 - - µs Start condition setup time tSU:STA 0.6 - - µs SDA hold time (vs. SCL falling edge) tHD:DAT 0 - - µs SDA setup time (vs. SCL rising edge) tSU:DAT 100 - - ns Stop condition setup time tSU:STO 0.6 - - µs Bus free time tBUF 1.3 - - µs Noise suppression pulse width tSP - - 50 ns Note *3. Reference data only, not tested. [I2C bus interface timing] VIH S DA VIL tBUF tLOW tR tHIGH tF tSP VIH SCL VIL tHD:STA tHD:DAT tSU:DAT tSU:STA tSU:STO Stop Start Start Stop Figure 10.1 Bus Timing 018015111-E-01 2019/8 - 9 -
10.2.2. AC Characteristics
Table 10.4 AC Characteristics (Standard Mode: fSCL ≤ 100kHz) Unless otherwise specified, AVDD = 2.7 ~ 3.6V, Ta = -40 ~ 85ºC Parameter Symbol Min. Typ. Max. Unit SCL clock frequency fSCL - - 100 kHz SCL clock high period tHIGH 4.0 - - µs SCL clock low period tLOW 4.7 - - µs SDA and SCL rise time (*2) tR - - 1.0 µs SDA and SCL fall time (*2) tF - - 0.3 µs Start condition hold time tHD:STA 4.0 - - µs Start condition setup time tSU:STA 4.7 - - µs SDA hold time (vs. SCL falling edge) tHD:DAT 0 - - µs SDA setup time (vs. SCL rising edge) tSU:DAT 250 - - ns Stop condition setup time tSU:STO 4.0 - - µs Bus free time tBUF 4.7 - - µs Note *2. Reference data only, not tested Table 10.5 AC Characteristics (Fast Mode: 100kHz ≤ fSCL ≤ 400kHz) Unless otherwise specified, AVDD = 2.7 ~ 3.6V, Ta = -40 ~ 85ºC Parameter Symbol Min. Typ. Max. Unit SCL clock frequency fSCL - - 400 kHz SCL clock high period tHIGH 0.6 - - µs SCL clock low period tLOW 1.3 - - µs SDA and SCL rise time (*3) tR - - 0.3 µs SDA and SCL fall time (*3) tF - - 0.3 µs Start condition hold time tHD:STA 0.6 - - µs Start condition setup time tSU:STA 0.6 - - µs SDA hold time (vs. SCL falling edge) tHD:DAT 0 - - µs SDA setup time (vs. SCL rising edge) tSU:DAT 100 - - ns Stop condition setup time tSU:STO 0.6 - - µs Bus free time tBUF 1.3 - - µs Noise suppression pulse width tSP - - 50 ns Note *3. Reference data only, not tested. [I2C bus interface timing] VIH S DA VIL tBUF tLOW tR tHIGH tF tSP VIH SCL VIL tHD:STA tHD:DAT tSU:DAT tSU:STA tSU:STO Stop Start Start Stop Figure 10.1 Bus Timing 018015111-E-01 2019/8 - 9 -
