Datasheet ADAU1787 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Four ADC, Two DAC, Low Power Codec with Audio DSPs |
| Pages / Page | 280 / 4 — ADAU1787. Data Sheet |
| Revision | A |
| File Format / Size | PDF / 1.9 Mb |
| Document Language | English |
ADAU1787. Data Sheet
Model Line for this Datasheet
Text Version of Document
link to page 128 link to page 130 link to page 131 link to page 133 link to page 134 link to page 135 link to page 136 link to page 137 link to page 139 link to page 141 link to page 143 link to page 145 link to page 147 link to page 149 link to page 151 link to page 153 link to page 154 link to page 155 link to page 156 link to page 157 link to page 158 link to page 160 link to page 161 link to page 163 link to page 163 link to page 164 link to page 165 link to page 166 link to page 167 link to page 168 link to page 169 link to page 170 link to page 171 link to page 172 link to page 173 link to page 174 link to page 174 link to page 175 link to page 176 link to page 176 link to page 177 link to page 177 link to page 178 link to page 179 link to page 180 link to page 181 link to page 182 link to page 183 link to page 184 link to page 185 link to page 186 link to page 187 link to page 188 link to page 189 link to page 189 link to page 190 link to page 191 link to page 192 link to page 193 link to page 194 link to page 195 link to page 196 link to page 197 link to page 198 link to page 199 link to page 167 link to page 200
ADAU1787 Data Sheet
Fast to Slow Decimator Channel 5 Input Routing Register ... 128 FastDSP Modulo N Counter for Lower Rate Conditional Fast to Slow Decimator Channel 6 Input Routing Register ... 130 Execution Register ... 167 Fast to Slow Decimator Channel 7 Input Routing Register ... 131 FastDSP Generic Conditional Execution Registers ... 168 Slow to Fast Interpolator Sample Rates Channel 0 and FastDSP Safeload Address Register.. 169 Channel 1 Register ... 133 FastDSP Safeload Parameter 0 Value Registers .. 169 Slow to Fast Interpolator Sample Rates Channel 2 and FastDSP Safeload Parameter 1 Value Registers .. 170 Channel 3 Register ... 134 FastDSP Safeload Parameter 2 Value Registers .. 171 Slow to Fast Interpolator Sample Rates Channel 4 and FastDSP Safeload Parameter 3 Value Registers .. 172 Channel 5 Register ... 135 FastDSP Safeload Parameter 4 Value Registers .. 173 Slow to Fast Interpolator Sample Rates Channel 6 and Channel 7 Register ... 136 FastDSP Safeload Update Register ... 174 Slow to Fast Interpolator Channel 0 Input Routing Register SigmaDSP Frame Rate Source Select Register ... 174 ... 137 SigmaDSP Run Register .. 175 Slow to Fast Interpolator Channel 1 Input Routing Register SigmaDSP Watchdog Controls Register.. 176 ... 139 SigmaDSP Watchdog Value Registers ... 176 Slow to Fast Interpolator Channel 2 Input Routing Register SigmaDSP Modulo Data Memory Start Position Registers 177 ... 141 SigmaDSP Fixed Frame Rate Divisor Registers ... 177 Slow to Fast Interpolator Channel 3 Input Routing Register ... 143 SigmaDSP Set Interrupts Register .. 178 Slow to Fast Interpolator Channel 4 Input Routing Register MultiPurpose Pin 0 and Pin 1 Mode Select Register ... 179 ... 145 MultiPurpose Pin 2 and Pin 3 Mode Select Register ... 180 Slow to Fast Interpolator Channel 5 Input Routing Register MultiPurpose Pin 4 and Pin 5 Mode Select Register ... 181 ... 147 MultiPurpose Pin 6 and Pin 7 Mode Select Register ... 182 Slow to Fast Interpolator Channel 6 Input Routing Register MultiPurpose Pin 8 and Pin 9 Mode Select Register ... 183 ... 149 MultiPurpose Pin 10 and Pin 11 Mode Select Register .. 184 Slow to Fast Interpolator Channel 7 Input Routing Register ... 151 General-Purpose Input Debounce Control and Master Clock Output Rate Selection Register ... 185 Input ASRC Control, Source, and Rate Selection Register . 153 General-Purpose Outputs Control Pin 0 to Pin 7 Register ... 186 Input ASRC Channel 0 and Channel 1 Input Routing Register ... 154 General-Purpose Outputs Control Pin 8 to Pin 10 Register ... 187 Input ASRC Channel 2 and Channel 3 Input Routing Register FSYNC_0 Pin Controls Register .. 188 ... 155 BCLK_0 Pin Controls Register ... 189 Output ASRC Control Register .. 156 SDATAO_0 Pin Control Register ... 189 Output ASRC Channel 0 Input Routing Register .. 157 SDATAI_0 Pin Controls Register ... 190 Output ASRC Channel 1 Input Routing Register .. 158 FSYNC_1 Pin Controls Register .. 191 Output ASRC Channel 2 Input Routing Register .. 160 BCLK_1 Pin Controls Register ... 192 Output ASRC Channel 3 Input Routing Register .. 161 SDATAO_1 Pin Controls Register ... 193 FastDSP Run Register .. 163 SDATAI_1 Pin Controls Register ... 194 FastDSP Current Bank and Bank Ramping Controls Register DMIC_CLK0 Pin Controls Register .. 195 ... 163 DMIC_CLK1 Pin Controls Register .. 196 FastDSP Bank Ramping Stop Point Register .. 164 DMIC01 Pin Controls Register .. 197 FastDSP Bank Copying Register .. 165 DMIC23 Pin Controls Register .. 198 FastDSP Frame Rate Source Register ... 166 SDA/MISO Pin Controls Register ... 198 FastDSP Fixed Rate Division MSBs Register .. 166 IRQ Signaling and Clearing Register ... 199 FastDSP Fixed Rate Division LSBs Register ... 167 IRQ1 Masking Registers .. 200 Rev. A | Page 4 of 280 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE SPECIFICATIONS CRYSTAL AMPLIFIER SPECIFICATIONS DIGITAL INPUT AND OUTPUT SPECIFICATIONS POWER SUPPLY SPECIFICATIONS POWER-DOWN CURRENT TYPICAL POWER CONSUMPTION DIGITAL FILTERS DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION SYSTEM CLOCKING AND POWER-UP POWER-DOWN OPERATION AND OPTIONS EXAMPLE ADC TO DAC POWER-UP DVDD LDO REGULATOR CLOCK INITIALIZATION PLL Enabled Setup Control Port Access During Initialization PLL PLL Bypass Operation Input Clock Divider Integer Mode Fractional Mode MULTICHIP PHASE SYNCHRONIZATION CLOCK OUTPUT POWER SUPPLY SEQUENCING Power-Down Considerations SIGNAL ROUTING INPUT SIGNAL PATHS ANALOG INPUTS Phase Difference Various Signal Path ADAU1787 Input Impedance Analog Microphone Inputs Analog Line Inputs Precharging Input Capacitors Microphone Bias PGAs DIGITAL MICROPHONE INPUTS Digital Microphone Volume Control ADCs ADC Full-Scale Level Digital ADC Volume Control Filtering OUTPUT SIGNAL PATHS ANALOG OUTPUTS Headphone Output Line Outputs Pop and Click Suppression DACs DAC Full-Scale Level Digital DAC Volume Control and Filtering PDM OUTPUTS PDM Outputs Full-Scale Level PDM Outputs Volume Control and Filtering ASRCs INTERPOLATION AND DECIMATION BLOCKS SIGNAL LEVELS FastDSP CORE INSTRUCTIONS FILTER PRECISION FLAGS AND CONDITIONAL EXECUTION INPUT SOURCES POWER AND RUN CONTROL DATA MEMORY PARAMETERS PARAMETER BANK SWITCHING PARAMETER BANK COPYING PARAMETER MEMORY ACCESS FastDSP PARAMETER SAFELOAD SigmaDSP CORE Signal Processing Details Program Counter Watchdog Features Numeric Formats Numeric Format 5.23 Programming READ/WRITE DATA FORMATS SOFTWARE SAFELOAD FastDSP SAFELOAD PROGRAM RAM, PARAMETER RAM, AND DATA RAM PROGRAM RAM PARAMETER RAM DATA RAM POWER SAVING OPTIONS ADC Bias Current Control DAC Bias Current Control DAC Low Power Modes PLL Bypass SigmaDSP Clock Speed Control Asynchronous Sample Rate Converters Low Power Modes CONTROL PORT BURST MODE COMMUNICATION READING AND WRITING TO MEMORIES I2C PORT Addressing I2C Read and Write Operations SPI PORT R/WB Subaddress Data Bytes SELF BOOT EEPROM Size CRC Delay Boot Time MULTIPURPOSE PINS Interrupts Pin Controls SERIAL DATA PORTS APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS LAYOUT GROUNDING PCB STACKUP REGISTER SUMMARY REGISTER DETAILS ADI VENDOR ID REGISTER DEVICE ID REGISTERS REVISION CODE REGISTER ADC, DAC, HEADPHONE POWER CONTROLS REGISTER PLL, MICROPHONE BIAS, AND PGA POWER CONTROLS REGISTER DIGITAL MICROPHONE POWER CONTROLS REGISTER SERIAL PORT, PDM OUTPUT, AND DIGITAL MICROPHONE CLK POWER CONTROLS REGISTER DSP POWER CONTROLS REGISTER ASRC POWER CONTROLS REGISTER INTERPOLATOR POWER CONTROLS REGISTER DECIMATOR POWER CONTROLS REGISTER STATE RETENTION CONTROLS REGISTER CHIP POWER CONTROL REGISTER CLOCK CONTROL REGISTER PLL INPUT DIVIDER REGISTER PLL FEEDBACK INTEGER DIVIDER (LSBs REGISTER) PLL FEEDBACK INTEGER DIVIDER (MSBs REGISTER) PLL FRACTIONAL NUMERATOR VALUE (LSBs REGISTER) PLL FRACTIONAL NUMERATOR VALUE (MSBs REGISTER) PLL FRACTIONAL DENOMINATOR (LSBs REGISTER) PLL FRACTIONAL DENOMINATOR (MSBs REGISTER) PLL UPDATE REGISTER ADC SAMPLE RATE CONTROL REGISTER ADC IBIAS CONTROLS REGISTER ADC HPF CONTROL REGISTER ADC MUTE AND COMPENSATION CONTROL REGISTER ANALOG INPUT PRECHARGE TIME REGISTER ADC CHANNEL MUTES REGISTER ADC CHANNEL 0 VOLUME CONTROL REGISTER ADC CHANNEL 1 VOLUME CONTROL REGISTER ADC CHANNEL 2 VOLUME CONTROL REGISTER ADC CHANNEL 3 VOLUME CONTROL REGISTER PGA CHANNEL 0 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 0 GAIN CONTROL LSBs REGISTER PGA CHANNEL 1 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 1 GAIN CONTROL LSBS REGISTER PGA CHANNEL 2 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 2 GAIN CONTROL LSBS REGISTER PGA CHANNEL 3 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 3 GAIN CONTROL LSBs REGISTER PGA SLEW RATE AND GAIN LINK REGISTER MICROPHONE BIAS LEVEL AND CURRENT REGISTER DIGITAL MICROPHONE CLOCK RATE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 0 AND CHANNEL 1 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 2 AND CHANNEL 3 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 4 AND CHANNEL 5 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 6 AND CHANNEL 7 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGTIAL MICROPHONE VOLUME OPTIONS REGISTER DIGITAL MICROPHONE CHANNEL MUTE CONTROLS REGISTER DIGITAL MICROPHONE CHANNEL 0 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 1 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 2 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 3 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 4 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 5 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 6 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 7 VOLUME CONTROL REGISTER DAC SAMPLE RATE, FILTERING, AND POWER CONTROLS REGISTER DAC VOLUME LINK, HIGH-PASS FILTER (HPF), AND MUTE CONTROLS REGISTER DAC CHANNEL 0 VOLUME REGISTER DAC CHANNEL 1 VOLUME REGISTER DAC CHANNEL 0 ROUTING REGISTER DAC CHANNEL 1 ROUTING REGISTER HEADPHONE CONTROL REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 0 AND CHANNEL 1 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 2 AND CHANNEL 3 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 4 AND CHANNEL 5 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 6 AND CHANNEL 7 REGISTER FAST TO SLOW DECIMATOR CHANNEL 0 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 1 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 2 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 3 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 4 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 5 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 6 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 7 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 0 AND CHANNEL 1 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 2 AND CHANNEL 3 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 4 AND CHANNEL 5 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 6 AND CHANNEL 7 REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 0 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 1 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 2 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 3 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 4 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 5 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 6 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 7 INPUT ROUTING REGISTER INPUT ASRC CONTROL, SOURCE, AND RATE SELECTION REGISTER INPUT ASRC CHANNEL 0 AND CHANNEL 1 INPUT ROUTING REGISTER INPUT ASRC CHANNEL 2 AND CHANNEL 3 INPUT ROUTING REGISTER OUTPUT ASRC CONTROL REGISTER OUTPUT ASRC CHANNEL 0 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 1 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 2 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 3 INPUT ROUTING REGISTER FastDSP RUN REGISTER FastDSP CURRENT BANK AND BANK RAMPING CONTROLS REGISTER FastDSP BANK RAMPING STOP POINT REGISTER FastDSP BANK COPYING REGISTER FastDSP FRAME RATE SOURCE REGISTER FastDSP FIXED RATE DIVISION MSBs REGISTER FastDSP FIXED RATE DIVISION LSBs REGISTER FastDSP MODULO N COUNTER FOR LOWER RATE CONDITIONAL EXECUTION REGISTER FastDSP GENERIC CONDITIONAL EXECUTION REGISTERS FastDSP SAFELOAD ADDRESS REGISTER FastDSP SAFELOAD PARAMETER 0 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 1 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 2 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 3 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 4 VALUE REGISTERS FastDSP SAFELOAD UPDATE REGISTER SigmaDSP FRAME RATE SOURCE SELECT REGISTER SigmaDSP RUN REGISTER SigmaDSP WATCHDOG CONTROLS REGISTER SigmaDSP WATCHDOG VALUE REGISTERS SigmaDSP MODULO DATA MEMORY START POSITION REGISTERS SigmaDSP FIXED FRAME RATE DIVISOR REGISTERS SigmaDSP SET INTERRUPTS REGISTER MULTIPURPOSE PIN 0 AND PIN 1 MODE SELECT REGISTER MULTIPURPOSE PIN 2 AND PIN 3 MODE SELECT REGISTER MULTIPURPOSE PIN 4 AND PIN 5 MODE SELECT REGISTER MULTIPURPOSE PIN 6 AND PIN 7 MODE SELECT REGISTER MULTIPURPOSE PIN 8 AND PIN 9 MODE SELECT REGISTER MULTIPURPOSE PIN 10 AND PIN 11 MODE SELECT REGISTER GENERAL-PURPOSE INPUT DEBOUNCE CONTROL AND MASTER CLOCK OUTPUT RATE SELECTION REGISTER GENERAL-PURPOSE OUTPUTS CONTROL PIN 0 TO PIN 7 REGISTER GENERAL-PURPOSE OUTPUTS CONTROL PIN 8 TO PIN 10 REGISTER FSYNC_0 PIN CONTROLS REGISTER BCLK_0 PIN CONTROLS REGISTER SDATAO_0 PIN CONTROL REGISTER SDATAI_0 PIN CONTROLS REGISTER FSYNC_1 PIN CONTROLS REGISTER BCLK_1 PIN CONTROLS REGISTER SDATAO_1 PIN CONTROLS REGISTER SDATAI_1 PIN CONTROLS REGISTER DMIC_CLK0 PIN CONTROLS REGISTER DMIC_CLK1 PIN CONTROLS REGISTER DMIC01 PIN CONTROLS REGISTER DMIC23 PIN CONTROLS REGISTER SDA/MISO PIN CONTROLS REGISTER IRQ SIGNALING AND CLEARING REGISTER IRQ1 MASKING REGISTERS IRQ2 MASKING REGISTERS CHIP RESETS REGISTER FastDSP CURRENT LAMBDA REGISTER CHIP STATUS 1 REGISTER CHIP STATUS 2 REGISTER GENERAL-PURPOSE INPUT READ 0 TO INPUT READ 7 REGISTER GENERAL-PURPOSE INPUT READ 8 TO INPUT READ 10 REGISTER DSP STATUS REGISTER IRQ1 STATUS 1 REGISTER IRQ1 STATUS 2 REGISTER IRQ1 STATUS 3 REGISTER IRQ2 STATUS 1 REGISTER IRQ2 STATUS 2 REGISTER IRQ2 STATUS 3 REGISTER SERIAL PORT 0 CONTROL 1 REGISTER SERIAL PORT 0 CONTROL 2 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 0 (LEFT REGISTER) SERIAL PORT 0 OUTPUT ROUTING SLOT 1 (RIGHT REGISTER) SERIAL PORT 0 OUTPUT ROUTING SLOT 2 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 3 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 4 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 5 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 6 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 7 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 8 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 9 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 10 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 11 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 12 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 13 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 14 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 15 REGISTER SERIAL PORT 1 CONTROL 1 REGISTER SERIAL PORT 1 CONTROL 2 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 0 (LEFT REGISTER) SERIAL PORT 1 OUTPUT ROUTING SLOT 1 (RIGHT REGISTER) SERIAL PORT 1 OUTPUT ROUTING SLOT 2 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 3 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 4 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 5 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 6 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 7 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 8 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 9 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 10 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 11 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 12 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 13 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 14 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 15 REGISTER MP12 PIN CONTROL REGISTER SELFBOOT PIN CONTROLS REGISTER SW_EN PIN CONTROLS REGISTER PDM SAMPLE RATE AND FILTERING CONTROL REGISTER PDM MUTING, HIGH-PASS, AND VOLUME OPTIONS REGISTER PDM OUTPUT CHANNEL 0 VOLUME REGISTER PDM OUTPUT CHANNEL 1 VOLUME REGISTER PDM OUTPUT CHANNEL 0 ROUTING REGISTER PDM OUTPUT CHANNEL 1 ROUTING REGISTER OUTLINE DIMENSIONS ORDERING GUIDE
ADAU1787 Data Sheet
Fast to Slow Decimator Channel 5 Input Routing Register ... 128 FastDSP Modulo N Counter for Lower Rate Conditional Fast to Slow Decimator Channel 6 Input Routing Register ... 130 Execution Register ... 167 Fast to Slow Decimator Channel 7 Input Routing Register ... 131 FastDSP Generic Conditional Execution Registers ... 168 Slow to Fast Interpolator Sample Rates Channel 0 and FastDSP Safeload Address Register.. 169 Channel 1 Register ... 133 FastDSP Safeload Parameter 0 Value Registers .. 169 Slow to Fast Interpolator Sample Rates Channel 2 and FastDSP Safeload Parameter 1 Value Registers .. 170 Channel 3 Register ... 134 FastDSP Safeload Parameter 2 Value Registers .. 171 Slow to Fast Interpolator Sample Rates Channel 4 and FastDSP Safeload Parameter 3 Value Registers .. 172 Channel 5 Register ... 135 FastDSP Safeload Parameter 4 Value Registers .. 173 Slow to Fast Interpolator Sample Rates Channel 6 and Channel 7 Register ... 136 FastDSP Safeload Update Register ... 174 Slow to Fast Interpolator Channel 0 Input Routing Register SigmaDSP Frame Rate Source Select Register ... 174 ... 137 SigmaDSP Run Register .. 175 Slow to Fast Interpolator Channel 1 Input Routing Register SigmaDSP Watchdog Controls Register.. 176 ... 139 SigmaDSP Watchdog Value Registers ... 176 Slow to Fast Interpolator Channel 2 Input Routing Register SigmaDSP Modulo Data Memory Start Position Registers 177 ... 141 SigmaDSP Fixed Frame Rate Divisor Registers ... 177 Slow to Fast Interpolator Channel 3 Input Routing Register ... 143 SigmaDSP Set Interrupts Register .. 178 Slow to Fast Interpolator Channel 4 Input Routing Register MultiPurpose Pin 0 and Pin 1 Mode Select Register ... 179 ... 145 MultiPurpose Pin 2 and Pin 3 Mode Select Register ... 180 Slow to Fast Interpolator Channel 5 Input Routing Register MultiPurpose Pin 4 and Pin 5 Mode Select Register ... 181 ... 147 MultiPurpose Pin 6 and Pin 7 Mode Select Register ... 182 Slow to Fast Interpolator Channel 6 Input Routing Register MultiPurpose Pin 8 and Pin 9 Mode Select Register ... 183 ... 149 MultiPurpose Pin 10 and Pin 11 Mode Select Register .. 184 Slow to Fast Interpolator Channel 7 Input Routing Register ... 151 General-Purpose Input Debounce Control and Master Clock Output Rate Selection Register ... 185 Input ASRC Control, Source, and Rate Selection Register . 153 General-Purpose Outputs Control Pin 0 to Pin 7 Register ... 186 Input ASRC Channel 0 and Channel 1 Input Routing Register ... 154 General-Purpose Outputs Control Pin 8 to Pin 10 Register ... 187 Input ASRC Channel 2 and Channel 3 Input Routing Register FSYNC_0 Pin Controls Register .. 188 ... 155 BCLK_0 Pin Controls Register ... 189 Output ASRC Control Register .. 156 SDATAO_0 Pin Control Register ... 189 Output ASRC Channel 0 Input Routing Register .. 157 SDATAI_0 Pin Controls Register ... 190 Output ASRC Channel 1 Input Routing Register .. 158 FSYNC_1 Pin Controls Register .. 191 Output ASRC Channel 2 Input Routing Register .. 160 BCLK_1 Pin Controls Register ... 192 Output ASRC Channel 3 Input Routing Register .. 161 SDATAO_1 Pin Controls Register ... 193 FastDSP Run Register .. 163 SDATAI_1 Pin Controls Register ... 194 FastDSP Current Bank and Bank Ramping Controls Register DMIC_CLK0 Pin Controls Register .. 195 ... 163 DMIC_CLK1 Pin Controls Register .. 196 FastDSP Bank Ramping Stop Point Register .. 164 DMIC01 Pin Controls Register .. 197 FastDSP Bank Copying Register .. 165 DMIC23 Pin Controls Register .. 198 FastDSP Frame Rate Source Register ... 166 SDA/MISO Pin Controls Register ... 198 FastDSP Fixed Rate Division MSBs Register .. 166 IRQ Signaling and Clearing Register ... 199 FastDSP Fixed Rate Division LSBs Register ... 167 IRQ1 Masking Registers .. 200 Rev. A | Page 4 of 280 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE SPECIFICATIONS CRYSTAL AMPLIFIER SPECIFICATIONS DIGITAL INPUT AND OUTPUT SPECIFICATIONS POWER SUPPLY SPECIFICATIONS POWER-DOWN CURRENT TYPICAL POWER CONSUMPTION DIGITAL FILTERS DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION SYSTEM CLOCKING AND POWER-UP POWER-DOWN OPERATION AND OPTIONS EXAMPLE ADC TO DAC POWER-UP DVDD LDO REGULATOR CLOCK INITIALIZATION PLL Enabled Setup Control Port Access During Initialization PLL PLL Bypass Operation Input Clock Divider Integer Mode Fractional Mode MULTICHIP PHASE SYNCHRONIZATION CLOCK OUTPUT POWER SUPPLY SEQUENCING Power-Down Considerations SIGNAL ROUTING INPUT SIGNAL PATHS ANALOG INPUTS Phase Difference Various Signal Path ADAU1787 Input Impedance Analog Microphone Inputs Analog Line Inputs Precharging Input Capacitors Microphone Bias PGAs DIGITAL MICROPHONE INPUTS Digital Microphone Volume Control ADCs ADC Full-Scale Level Digital ADC Volume Control Filtering OUTPUT SIGNAL PATHS ANALOG OUTPUTS Headphone Output Line Outputs Pop and Click Suppression DACs DAC Full-Scale Level Digital DAC Volume Control and Filtering PDM OUTPUTS PDM Outputs Full-Scale Level PDM Outputs Volume Control and Filtering ASRCs INTERPOLATION AND DECIMATION BLOCKS SIGNAL LEVELS FastDSP CORE INSTRUCTIONS FILTER PRECISION FLAGS AND CONDITIONAL EXECUTION INPUT SOURCES POWER AND RUN CONTROL DATA MEMORY PARAMETERS PARAMETER BANK SWITCHING PARAMETER BANK COPYING PARAMETER MEMORY ACCESS FastDSP PARAMETER SAFELOAD SigmaDSP CORE Signal Processing Details Program Counter Watchdog Features Numeric Formats Numeric Format 5.23 Programming READ/WRITE DATA FORMATS SOFTWARE SAFELOAD FastDSP SAFELOAD PROGRAM RAM, PARAMETER RAM, AND DATA RAM PROGRAM RAM PARAMETER RAM DATA RAM POWER SAVING OPTIONS ADC Bias Current Control DAC Bias Current Control DAC Low Power Modes PLL Bypass SigmaDSP Clock Speed Control Asynchronous Sample Rate Converters Low Power Modes CONTROL PORT BURST MODE COMMUNICATION READING AND WRITING TO MEMORIES I2C PORT Addressing I2C Read and Write Operations SPI PORT R/WB Subaddress Data Bytes SELF BOOT EEPROM Size CRC Delay Boot Time MULTIPURPOSE PINS Interrupts Pin Controls SERIAL DATA PORTS APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS LAYOUT GROUNDING PCB STACKUP REGISTER SUMMARY REGISTER DETAILS ADI VENDOR ID REGISTER DEVICE ID REGISTERS REVISION CODE REGISTER ADC, DAC, HEADPHONE POWER CONTROLS REGISTER PLL, MICROPHONE BIAS, AND PGA POWER CONTROLS REGISTER DIGITAL MICROPHONE POWER CONTROLS REGISTER SERIAL PORT, PDM OUTPUT, AND DIGITAL MICROPHONE CLK POWER CONTROLS REGISTER DSP POWER CONTROLS REGISTER ASRC POWER CONTROLS REGISTER INTERPOLATOR POWER CONTROLS REGISTER DECIMATOR POWER CONTROLS REGISTER STATE RETENTION CONTROLS REGISTER CHIP POWER CONTROL REGISTER CLOCK CONTROL REGISTER PLL INPUT DIVIDER REGISTER PLL FEEDBACK INTEGER DIVIDER (LSBs REGISTER) PLL FEEDBACK INTEGER DIVIDER (MSBs REGISTER) PLL FRACTIONAL NUMERATOR VALUE (LSBs REGISTER) PLL FRACTIONAL NUMERATOR VALUE (MSBs REGISTER) PLL FRACTIONAL DENOMINATOR (LSBs REGISTER) PLL FRACTIONAL DENOMINATOR (MSBs REGISTER) PLL UPDATE REGISTER ADC SAMPLE RATE CONTROL REGISTER ADC IBIAS CONTROLS REGISTER ADC HPF CONTROL REGISTER ADC MUTE AND COMPENSATION CONTROL REGISTER ANALOG INPUT PRECHARGE TIME REGISTER ADC CHANNEL MUTES REGISTER ADC CHANNEL 0 VOLUME CONTROL REGISTER ADC CHANNEL 1 VOLUME CONTROL REGISTER ADC CHANNEL 2 VOLUME CONTROL REGISTER ADC CHANNEL 3 VOLUME CONTROL REGISTER PGA CHANNEL 0 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 0 GAIN CONTROL LSBs REGISTER PGA CHANNEL 1 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 1 GAIN CONTROL LSBS REGISTER PGA CHANNEL 2 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 2 GAIN CONTROL LSBS REGISTER PGA CHANNEL 3 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 3 GAIN CONTROL LSBs REGISTER PGA SLEW RATE AND GAIN LINK REGISTER MICROPHONE BIAS LEVEL AND CURRENT REGISTER DIGITAL MICROPHONE CLOCK RATE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 0 AND CHANNEL 1 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 2 AND CHANNEL 3 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 4 AND CHANNEL 5 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 6 AND CHANNEL 7 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGTIAL MICROPHONE VOLUME OPTIONS REGISTER DIGITAL MICROPHONE CHANNEL MUTE CONTROLS REGISTER DIGITAL MICROPHONE CHANNEL 0 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 1 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 2 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 3 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 4 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 5 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 6 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 7 VOLUME CONTROL REGISTER DAC SAMPLE RATE, FILTERING, AND POWER CONTROLS REGISTER DAC VOLUME LINK, HIGH-PASS FILTER (HPF), AND MUTE CONTROLS REGISTER DAC CHANNEL 0 VOLUME REGISTER DAC CHANNEL 1 VOLUME REGISTER DAC CHANNEL 0 ROUTING REGISTER DAC CHANNEL 1 ROUTING REGISTER HEADPHONE CONTROL REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 0 AND CHANNEL 1 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 2 AND CHANNEL 3 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 4 AND CHANNEL 5 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 6 AND CHANNEL 7 REGISTER FAST TO SLOW DECIMATOR CHANNEL 0 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 1 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 2 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 3 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 4 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 5 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 6 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 7 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 0 AND CHANNEL 1 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 2 AND CHANNEL 3 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 4 AND CHANNEL 5 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 6 AND CHANNEL 7 REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 0 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 1 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 2 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 3 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 4 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 5 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 6 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 7 INPUT ROUTING REGISTER INPUT ASRC CONTROL, SOURCE, AND RATE SELECTION REGISTER INPUT ASRC CHANNEL 0 AND CHANNEL 1 INPUT ROUTING REGISTER INPUT ASRC CHANNEL 2 AND CHANNEL 3 INPUT ROUTING REGISTER OUTPUT ASRC CONTROL REGISTER OUTPUT ASRC CHANNEL 0 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 1 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 2 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 3 INPUT ROUTING REGISTER FastDSP RUN REGISTER FastDSP CURRENT BANK AND BANK RAMPING CONTROLS REGISTER FastDSP BANK RAMPING STOP POINT REGISTER FastDSP BANK COPYING REGISTER FastDSP FRAME RATE SOURCE REGISTER FastDSP FIXED RATE DIVISION MSBs REGISTER FastDSP FIXED RATE DIVISION LSBs REGISTER FastDSP MODULO N COUNTER FOR LOWER RATE CONDITIONAL EXECUTION REGISTER FastDSP GENERIC CONDITIONAL EXECUTION REGISTERS FastDSP SAFELOAD ADDRESS REGISTER FastDSP SAFELOAD PARAMETER 0 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 1 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 2 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 3 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 4 VALUE REGISTERS FastDSP SAFELOAD UPDATE REGISTER SigmaDSP FRAME RATE SOURCE SELECT REGISTER SigmaDSP RUN REGISTER SigmaDSP WATCHDOG CONTROLS REGISTER SigmaDSP WATCHDOG VALUE REGISTERS SigmaDSP MODULO DATA MEMORY START POSITION REGISTERS SigmaDSP FIXED FRAME RATE DIVISOR REGISTERS SigmaDSP SET INTERRUPTS REGISTER MULTIPURPOSE PIN 0 AND PIN 1 MODE SELECT REGISTER MULTIPURPOSE PIN 2 AND PIN 3 MODE SELECT REGISTER MULTIPURPOSE PIN 4 AND PIN 5 MODE SELECT REGISTER MULTIPURPOSE PIN 6 AND PIN 7 MODE SELECT REGISTER MULTIPURPOSE PIN 8 AND PIN 9 MODE SELECT REGISTER MULTIPURPOSE PIN 10 AND PIN 11 MODE SELECT REGISTER GENERAL-PURPOSE INPUT DEBOUNCE CONTROL AND MASTER CLOCK OUTPUT RATE SELECTION REGISTER GENERAL-PURPOSE OUTPUTS CONTROL PIN 0 TO PIN 7 REGISTER GENERAL-PURPOSE OUTPUTS CONTROL PIN 8 TO PIN 10 REGISTER FSYNC_0 PIN CONTROLS REGISTER BCLK_0 PIN CONTROLS REGISTER SDATAO_0 PIN CONTROL REGISTER SDATAI_0 PIN CONTROLS REGISTER FSYNC_1 PIN CONTROLS REGISTER BCLK_1 PIN CONTROLS REGISTER SDATAO_1 PIN CONTROLS REGISTER SDATAI_1 PIN CONTROLS REGISTER DMIC_CLK0 PIN CONTROLS REGISTER DMIC_CLK1 PIN CONTROLS REGISTER DMIC01 PIN CONTROLS REGISTER DMIC23 PIN CONTROLS REGISTER SDA/MISO PIN CONTROLS REGISTER IRQ SIGNALING AND CLEARING REGISTER IRQ1 MASKING REGISTERS IRQ2 MASKING REGISTERS CHIP RESETS REGISTER FastDSP CURRENT LAMBDA REGISTER CHIP STATUS 1 REGISTER CHIP STATUS 2 REGISTER GENERAL-PURPOSE INPUT READ 0 TO INPUT READ 7 REGISTER GENERAL-PURPOSE INPUT READ 8 TO INPUT READ 10 REGISTER DSP STATUS REGISTER IRQ1 STATUS 1 REGISTER IRQ1 STATUS 2 REGISTER IRQ1 STATUS 3 REGISTER IRQ2 STATUS 1 REGISTER IRQ2 STATUS 2 REGISTER IRQ2 STATUS 3 REGISTER SERIAL PORT 0 CONTROL 1 REGISTER SERIAL PORT 0 CONTROL 2 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 0 (LEFT REGISTER) SERIAL PORT 0 OUTPUT ROUTING SLOT 1 (RIGHT REGISTER) SERIAL PORT 0 OUTPUT ROUTING SLOT 2 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 3 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 4 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 5 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 6 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 7 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 8 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 9 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 10 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 11 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 12 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 13 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 14 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 15 REGISTER SERIAL PORT 1 CONTROL 1 REGISTER SERIAL PORT 1 CONTROL 2 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 0 (LEFT REGISTER) SERIAL PORT 1 OUTPUT ROUTING SLOT 1 (RIGHT REGISTER) SERIAL PORT 1 OUTPUT ROUTING SLOT 2 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 3 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 4 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 5 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 6 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 7 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 8 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 9 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 10 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 11 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 12 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 13 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 14 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 15 REGISTER MP12 PIN CONTROL REGISTER SELFBOOT PIN CONTROLS REGISTER SW_EN PIN CONTROLS REGISTER PDM SAMPLE RATE AND FILTERING CONTROL REGISTER PDM MUTING, HIGH-PASS, AND VOLUME OPTIONS REGISTER PDM OUTPUT CHANNEL 0 VOLUME REGISTER PDM OUTPUT CHANNEL 1 VOLUME REGISTER PDM OUTPUT CHANNEL 0 ROUTING REGISTER PDM OUTPUT CHANNEL 1 ROUTING REGISTER OUTLINE DIMENSIONS ORDERING GUIDE
