Datasheet ADAU1372 (Analog Devices) - 7

Data Sheet ADAU1372 Parameter Test Conditions/Comments Min Typ Max Unit
THD + N 20 Hz to 20 kHz, −1 dBFS input dB AVDD = 1.8 V −96 dB AVDD = 3.3 V −96 dB Gain Error Line output mode ±0.25 dB Headphone Mode Dynamic Range1 20 Hz to 20 kHz, −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 104 dB AVDD = 3.3 V 107 dB With Flat 20 Hz to 20 kHz Filter AVDD = 1.8 V 102 dB AVDD = 3.3 V 104 dB SNR2 20 Hz to 20 kHz With A-Weighted Filter (RMS) AVDD = 1.8 V 105 dB AVDD = 3.3 V 108 dB With Flat 20 Hz to 20 kHz Filter AVDD = 1.8 V 103 dB AVDD = 3.3 V 106 dB Interchannel Gain Mismatch 75 mdB THD + N 32 Ω Load −1 dBFS, AVDD = 1.8 V, output power = 27 mW −75 dB −1 dBFS, AVDD = 3.3 V, output power = 90 mW −83 dB 24 Ω Load −2 dBFS, AVDD = 1.8 V, output power = 28 mW −75 dB −1 dBFS, AVDD = 3.3 V, output power = 118 mW −77 dB 16 Ω Load −3 dBFS, AVDD = 1.8 V, output power = 33 mW −75 dB −1 dBFS, AVDD = 3.3 V, output power = 175 mW −83 dB Gain Error ±0.25 dB Headphone Output Power 32 Ω Load AVDD = 1.8 V, <0.1% THD + N 32.5 mW AVDD = 3.3 V, <0.1% THD + N 111.8 mW 24 Ω Load AVDD = 1.8 V, <0.1% THD + N 37.6 mW AVDD = 3.3 V, <0.1% THD + N 148.3 mW 16 Ω Load AVDD = 1.8 V, <0.1% THD + N 41.5 mW AVDD = 3.3 V, <0.1% THD + N 189.2 mW Offset Error ±0.1 mV Interchannel Isolation 1 kHz, 0 dBFS input signal 100 dB PSRR CM capacitor = 22 µF, 100 mV p-p at 1 kHz 73 dB CM REFERENCE CM pin Common-Mode Reference Output AVDD/2 V Common-Mode Source Impedance 5 kΩ REGULATOR Line Regulation 1 mV/V Load Regulation 6 mV/mA 1 Dynamic range is the ratio of the sum of the noise and harmonic power in the band of interest with a −60 dBFS signal present to the full-scale power level in decibels. 2 SNR is the ratio of the sum of all noise power in the band of interest with no signal present to the full-scale power level in decibels. 3 These specifications are tested with a 4.7 µF decoupling capacitor and 5.0 kΩ load on the MICBIASx pins.
CRYSTAL AMPLIFIER SPECIFICATIONS
Supply voltages AVDD = IOVDD = 1.8 V, DVDD = 1.1 V, unless otherwise noted.
Table 2. Parameter Min Typ Max Unit
Jitter 270 500 ps Frequency Range 8 27 MHz Load Capacitance 20 pF Rev. 0 | Page 7 of 92 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ANALOG PERFORMANCE SPECIFICATIONS CRYSTAL AMPLIFIER SPECIFICATIONS DIGITAL INPUT/OUTPUT SPECIFICATIONS POWER SUPPLY SPECIFICATIONS TYPICAL POWER CONSUMPTION DIGITAL FILTERS DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SYSTEM CLOCKING AND POWER-UP INITIALIZATION CLOCK INITIALIZATION PLL Bypass Setup PLL Enabled Setup Control Port Access During Initialization PLL Input Clock Divider Integer Mode Fractional Mode CLOCK OUTPUT POWER SEQUENCING Power-Down Considerations SIGNAL ROUTING INPUT SIGNAL PATHS ANALOG INPUTS Signal Polarity Input Impedance Analog Microphone Inputs Analog Line Inputs Precharging Input Capacitors Microphone Bias DIGITAL MICROPHONE INPUT ANALOG-TO-DIGITAL CONVERTERS ADC Full-Scale Level Digital ADC Volume Control High-Pass Filter OUTPUT SIGNAL PATHS ANALOG OUTPUTS Headphone Output Headphone Output Power-Up Sequencing Ground Centered Headphone Configuration Pop and Click Suppression Line Outputs DIGITAL-TO-ANALOG CONVERTERS DAC Full-Scale Level Digital DAC Volume Control ASYNCHRONOUS SAMPLE RATE CONVERTERS CONTROL PORT BURST MODE COMMUNICATION I2C PORT Addressing I2C Read and Write Operations SPI PORT Read/Write Subaddress Data Bytes BURST MODE COMMUNICATION MULTIPURPOSE PINS PUSH-BUTTON VOLUME CONTROLS MUTE TALKTHROUGH MODE SERIAL DATA INPUT/OUTPUT PORTS SERIAL PORT INITIALIZATION TRISTATING UNUSED CHANNELS APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS LAYOUT GROUNDING EXPOSED PAD PCB DESIGN SYSTEM BLOCK DIAGRAM REGISTER SUMMARY: LOW LATENCY CODEC CLOCK CONTROL REGISTER PLL DENOMINATOR MSB REGISTER PLL DENOMINATOR LSB REGISTER PLL NUMERATOR MSB REGISTER PLL NUMERATOR LSB REGISTER PLL INTEGER SETTING REGISTER PLL LOCK FLAG REGISTER CLKOUT SETTING SELECTION REGISTER REGULATOR CONTROL REGISTER DAC INPUT SELECT REGISTER SERIAL DATA OUTPUT 0/SERIAL DATA OUTPUT 1 INPUT SELECT REGISTER SERIAL DATA OUTPUT 2/SERIAL DATA OUTPUT 3 INPUT SELECT REGISTER SERIAL DATA OUTPUT 4/SERIAL DATA OUTPUT 5 INPUT SELECT REGISTER SERIAL DATA OUTPUT 6/SERIAL DATA OUTPUT 7 INPUT SELECT REGISTER ADC_SDATA0/ADC_SDATA1 CHANNEL SELECT REGISTER OUTPUT ASRC0/OUTPUT ASRC1 SOURCE REGISTER OUTPUT ASRC2/OUTPUT ASRC3 SOURCE REGISTER INPUT ASRC CHANNEL SELECT REGISTER ADC CONTROL 0 REGISTER ADC CONTROL 1 REGISTER ADC CONTROL 2 REGISTER ADC CONTROL 3 REGISTER ADC0 VOLUME CONTROL REGISTER ADC1 VOLUME CONTROL REGISTER ADC2 VOLUME CONTROL REGISTER ADC3 VOLUME CONTROL REGISTER PGA CONTROL 0 REGISTER PGA CONTROL 1 REGISTER PGA CONTROL 2 REGISTER PGA CONTROL 3 REGISTER PGA SLEW CONTROL REGISTER PGA 10 dB GAIN BOOST REGISTER INPUT AND OUTPUT CAPACITOR CHARGING REGISTER ADC TO DAC TALKTHROUGH BYPASS PATH REGISTER TALKTHROUGH BYPASS GAIN FOR ADC0 REGISTER TALKTHROUGH BYPASS GAIN FOR ADC1 REGISTER MICBIAS CONTROL REGISTER DAC CONTROL 1 REGISTER DAC0 VOLUME CONTROL REGISTER DAC1 VOLUME CONTROL REGISTER HEADPHONE OUTPUT MUTES REGISTER SERIAL PORT CONTROL 0 REGISTER SERIAL PORT CONTROL 1 REGISTER TDM OUTPUT CHANNEL DISABLE REGISTER MP0 FUNCTION SETTING REGISTER MP1 FUNCTION SETTING REGISTER MP4 FUNCTION SETTING REGISTER MP5 FUNCTION SETTING REGISTER MP6 FUNCTION SETTING REGISTER PUSH-BUTTON VOLUME SETTINGS REGISTER PUSH-BUTTON VOLUME CONTROL ASSIGNMENT REGISTER DEBOUNCE MODES REGISTER HEADPHONE LINE OUTPUT SELECT REGISTER DECIMATOR POWER CONTROL REGISTER ASRC INTERPOLATOR AND DAC MODULATOR POWER CONTROL REGISTER ANALOG BIAS CONTROL 0 REGISTER ANALOG BIAS CONTROL 1 REGISTER DIGITAL PIN PULL-UP CONTROL 0 REGISTER DIGITAL PIN PULL-UP CONTROL 1 REGISTER DIGITAL PIN PULL-DOWN CONTROL 2 REGISTER DIGITAL PIN PULL-DOWN CONTROL 3 REGISTER DIGITAL PIN DRIVE STRENGTH CONTROL 4 REGISTER DIGITAL PIN DRIVE STRENGTH CONTROL 5 REGISTER OUTLINE DIMENSIONS ORDERING GUIDE