Datasheet ADAU1328 (Analog Devices)

2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec Data Sheet ADAU1328 FEATURES GENERAL DESCRIPTION PLL generated or direct master clock
The ADAU1328 is a high performance, single-chip codec that
Low EMI design
provides two analog-to-digital converters (ADCs) with differential
108 dB DAC/107 dB ADC dynamic range and SNR
input and eight digital-to-analog converters (DACs) with
−94 dB THD + N
single-ended output using the Analog Devices, Inc. patented
Single 3.3 V supply
multibit sigma-delta (Σ-Δ) architecture. An SPI port is included,
Tolerance for 5 V logic inputs
allowing a microcontrol er to adjust volume and many other
Supports 24 bits and 8 kHz to 192 kHz sample rates
parameters. The ADAU1328 operates from 3.3 V digital and
Differential ADC input
analog supplies. The ADAU1328 is available in a 48-lead
Single-ended DAC output
(single-ended output) LQFP. Other members of this family
Log volume control with autoramp function
include a differential DAC output version.
SPI® controllable for flexibility Software controllable clickless mute
The ADAU1328 is designed for low EMI. This consideration is
Software power-down
apparent in both the system and circuit design architectures.
Right justified, left justified, I2S and TDM modes
By using the on-board PLL to derive the master clock from the
Master and slave modes up to 16-channel in/out
LR clock or from an external crystal, the ADAU1328 eliminates
48-lead LQFP
the need for a separate high frequency master clock and can also be used with a suppressed bit clock. The digital-to-analog
APPLICATIONS
and analog-to-digital converters are designed using the latest ADI continuous time architectures to further minimize EMI. By
Home theater systems
using 3.3 V supplies, power consumption is minimized, further
Set-top boxes
reducing emissions.
Digital audio effects processors FUNCTIONAL BLOCK DIAGRAM DIGITAL AUDIO INPUT/OUTPUT ADAU1328 SERIAL DATA PORT DAC DAC SDATA SDATA DAC OUT IN DIGITAL ADC CLOCKS FILTER DAC DEC AND FILTER VOLUME 48/96/ DAC ADC CONTROL 192kHz TIMING MANAGEMENT AND CONTROL DAC (CLOCK AND PLL) DAC DAC CONTROL PRECISION PORT VOLTAGE SPI REFERENCE 12.488MHz 6.144MHz CONTROL DATA
001
INPUT/OUTPUT
06102- Figure 1.
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Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Test Conditions Analog Performance Specifications Crystal Oscillator Specifications Digital Input/Output Specifications Power Supply Specifications Digital Filters Timing Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Analog-to-Digital Converters (ADCs) Digital-to-Analog Converters (DACs) Clock Signals Reset and Power-Down Serial Control Port Power Supply and Voltage Reference Serial Data Ports—Data Format Time-Division Multiplexed (TDM) Modes Daisy-Chain Mode Control Registers Definitions PLL and Clock Control Registers DAC Control Registers ADC Control Registers Additional Modes Application Circuits Outline Dimensions Ordering Guide