Datasheet AD1939 (Analog Devices) - 9

Data Sheet AD1939 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS N P N P DD DD NC NC AV LF ADC2RN ADC2RP ADC2L ADC2L ADC1RN ADC1RP ADC1L ADC1L CM AV NC NC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AGND 1 48 AGND MCLKI/XI 2 47 FILTR MCLKO/XO 3 46 AGND AGND 4 45 AVDD AVDD 5 44 AGND OL3P 6 43 OR2N OL3N 7 42 OR2P AD1939 OR3P 8 41 TOP VIEW OL2N (Not to Scale) OR3N 9 40 OL2P DIFFERENTIAL OL4P 10 OUTPUT 39 OR1N OL4N 11 38 OR1P OR4P 12 37 OL1N OR4N 13 36 OL1P PD/RST 14 35 CLATCH DSDATA4 15 34 CCLK DGND 16 33 DGND 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 K K Y E K K N DD A3 A2 A1 SE V A2 A1 CI UT DD DV RCL PPL RCL CO DV DAT DAT DAT DBCL DRI DAT DAT ABCL
021
DL VSEN V AL NC = NO CONNECT DS DS DS VSU AS AS
06071- Figure 2. 64-Lead LQFP, Differential Output, Pin Configuration
Table 10. Pin Function Descriptions Pin No. In/Out Mnemonic Description
1 I AGND Analog Ground. 2 I MCLKI/XI Master Clock Input/Crystal Oscillator Input. 3 O MCLKO/XO Master Clock Output/Crystal Oscillator Output. 4 I AGND Analog Ground. 5 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 6 O OL3P DAC 3 Left Positive Output. 7 O OL3N DAC 3 Left Negative Output. 8 O OR3P DAC 3 Right Positive Output. 9 O OR3N DAC 3 Right Negative Output. 10 O OL4P DAC 4 Left Positive Output. 11 O OL4N DAC 4 Left Negative Output. 12 O OR4P DAC 4 Right Positive Output. 13 O OR4N DAC 4 Right Negative Output 14 I PD/R ST Power-Down Reset (Active Low). 15 I/O DSDATA4 DAC Serial Data Input 4. Data input to DAC4 data in/TDM DAC2 data out (dual-line mode)/AUX DAC2 data out (to external DAC2). 16 I DGND Digital Ground. 17 I DVDD Digital Power Supply. Connect to digital 3.3 V supply. 18 I/O DSDATA3 DAC Serial Data Input 3. Data input to DAC3 data in/TDM DAC2 data in (dual-line mode)/AUX ADC2 data in (from external ADC2). 19 I/O DSDATA2 DAC Serial Data Input 2. Data input to DAC2 data in/TDM DAC data out/AUX ADC1 data in (from external ADC1). 20 I DSDATA1 DAC Serial Data Input 1. Data input to DAC1 data in/TDM DAC data in/TDM data in. 21 I/O DBCLK Bit Clock for DACs. 22 I/O DLRCLK LR Clock for DACs. Rev. E | Page 9 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Test Conditions Analog Performance Specifications Crystal Oscillator Specifications Digital Input/Output Specifications Power Supply Specifications Digital Filters Timing Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Analog-to-Digital Converters (ADCs) Digital-to-Analog Converters (DACs) Clock Signals Reset and Power-Down Serial Control Port Power Supply and Voltage Reference Serial Data Ports—Data Format Time-Division Multiplexed (TDM) Modes Daisy-Chain Mode Control Registers Definitions PLL and Clock Control Registers DAC Control Registers ADC Control Registers Additional Modes Application Circuits Outline Dimensions Ordering Guide Automotive Products