Datasheet ADAV801 (Analog Devices) - 5

ADAV801 Parameter Min Typ Max Unit Comments
Crosstalk (EIAJ Method) −110 dB Phase Deviation 0.05 Degrees Mute Attenuation −95.625 dB Volume Control Step Size (256 Steps) 0.375 dB Group Delay 48 kHz 630 μs 96 kHz 155 μs 192 kHz 66 μs DAC LOW-PASS DIGITAL INTERPOLATION FILTER CHARACTERISTICS Pass-Band Frequency 20 kHz fS = 44.1 kHz 22 kHz fS = 48 kHz 42 kHz fS = 96 kHz Stop-Band Frequency 24 kHz fS = 44.1 kHz 26 kHz fS = 48 kHz 60 kHz fS = 96 kHz Stop-Band Attenuation 70 dB fS = 44.1 kHz 70 dB fS = 48 kHz 70 dB fS = 96 kHz Pass-Band Ripple ±0.002 dB fS = 44.1 kHz ±0.002 dB fS = 48 kHz ±0.005 dB fS = 96 kHz PLL SECTION Master Clock Input Frequency 27/54 MHz Generated System Clocks MCLKO 27/54 MHz SYSCLK1 256 768 × fS 256/384/512/768 × 32 kHz/ 44.1 kHz/48 kHz SYSCLK2 256 768 × fS 256/384/512/768 × 32 kHz/ 44.1 kHz/48 kHz SYSCLK3 256 512 × fS 256/512 × 32 kHz/44.1 kHz/ 48 kHz Jitter SYSCLK1 65 ps rms SYSCLK2 75 ps rms SYSCLK3 75 ps rms DIR SECTION Input Sample Frequency 27.2 200 kHz Differential Input Voltage 200 mV DIT SECTION Output Sample Frequency 27.2 200 kHz DIGITAL I/O Input Voltage High, VIH 2.0 DVDD V Input Voltage Low, VIL 0.8 V Input Leakage, IIH @ VIH = 3.3 V 10 μA Input Leakage, IIL @ VIL = 0 V 10 μA Output Voltage High, VOH @ IOH = 0.4 mA 2.4 V Output Voltage Low, VOL @ IOL = −2 mA 0.4 V Input Capacitance 15 pF Rev. A | Page 5 of 60 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TEST CONDITIONS ADAV801 SPECIFICATIONS TIMING SPECIFICATIONS TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS FUNCTIONAL DESCRIPTION ADC SECTION Programmable Gain Amplifier (PGA) Analog Σ-Δ Modulator Automatic Level Control (ALC) Attack Mode No Recovery Mode Normal Recovery Mode Limited Recovery Mode Selecting a Sample Rate DAC SECTION Selecting a Sample Rate SAMPLE RATE CONVERTER (SRC) FUNCTIONAL OVERVIEW Conceptual High Interpolation Model Hardware Model SRC Architecture PLL SECTION S/PDIF TRANSMITTER AND RECEIVER Serial Digital Audio Transmission Standards Receiver Section Transmitter Operation Autobuffering Interrupts SERIAL DATA PORTS Clocking Scheme Datapath INTERFACE CONTROL SPI INTERFACE BLOCK READS AND WRITES REGISTER DESCRIPTIONS SRC and Clock Control—Address 0000000 (0x00) S/PDIF Loopback Control—Address 0000011 (0x03) Playback Port Control—Address 0000100 (0x04) Auxiliary Input Port—Address 0000101 (0x05) Record Port Control—Address 0000110 (0x06) Auxiliary Output Port—Address 0000111 (0x07) Group Delay and Mute—Address 0001000 (0x08) Receiver Configuration 1—Address 0001001 (0x09) Receiver Configuration 2—Address 0001010 (0x0A) Receiver Buffer Configuration—Address 0001011 (0x0B) Transmitter Control—Address 0001100 (0x0C) Transmitter Buffer Configuration—Address 0001101 (0x0D) Channel Status Switch Buffer and Transmitter—Address 0001110 (0x0E) Transmitter Message Zeros Most Significant Byte—Address 0001111 (0x0F) Transmitter Message Zeros Least Significant Byte—Address 0010000 (0x10) Autobuffer—Address 0010001 (0x11) Sample Rate Ratio MSB—Address 0010010 (0x12) Sample Rate Ratio LSB—Address 0010011 (0x13) Preamble-C MSB—Address 0010100 (0x14) Preamble-C LSB—Address 0010101 (0x15) Preamble-D MSB—Address 0010110 (0x16) Preamble-D LSB—Address 0010111 (0x17) Receiver Error—Address 0011000 (0x18) Receiver Error Mask—Address 0011001 (0x19) Sample Rate Converter Error—Address 0011010 (0x1A) Sample Rate Converter Error Mask—Address 0011011 (0x1B) Interrupt Status—Address 0011100 (0x1C) Interrupt Status Mask—Address 0011101 (0x1D) Mute and De-Emphasis—Address 0011110 (0x1E) NonAudio Preamble Type—Address 0011111 (0x1F) Receiver Channel Status Buffer—Address 0100000 to Address 0110111 (0x20 to 0x37) Transmitter Channel Status Buffer—Address 0111000 to Address 1001111 (0x38 to 0x4F) Receiver User Bit Buffer Indirect Address— Address 1010000 (0x50) Receiver User Bit Buffer Data—Address 1010001 (0x51) Transmitter User Bit Buffer Indirect Address—Address 1010010 (0x52) Transmitter User Bit Buffer Data—Address 1010011 (0x53) Q Subcode CRCError Status—Address 1010100 (0x54) Q Subcode Buffer—Address 0x55 to Address 0x5E Datapath Control Register 1—Address 1100010 (0x62) Datapath Control Register 2—Address 1100011 (0x63) DAC Control Register 1—Address 1100100 (0x64) DAC Control Register 2—Address 1100101 (0x65) DAC Control Register 3—Address 1100110 (0x66) DAC Control Register 4—Address 1100111 (0x67) DAC Left Volume—Address 1101000 (0x68) DAC Right Volume—Address 1101001 (0x69) DAC Left Peak Volume—Address 1101010 (0x6A) DAC Right Peak Volume—Address 1101011 (0x6B) ADC Left Channel PGA Gain—Address 1101100 (0x6C) ADC Right Channel PGA Gain—Address 1101101 (0x6D) ADC Control Register 1—Address 1101110 (0x6E) ADC Control Register 2—Address 1101111 (0x6F) ADC Left Volume—Address 1110000 (0x70) ADC Right Volume—Address 1110001 (0x71) ADC Left Peak Volume—Address 1110010 (0x72) ADC Right Peak Volume—Address 1110011 (0x73) PLL Control Register 1—Address 1110100 (0x74) PLL Control Register 2—Address 1110101 (0x75) Internal Clocking Control Register 1—Address 1110110 (0x76) Internal Clocking Control Register 2—Address 1110111 (0x77) PLL Clock Source Register—Address 1111000 (0x78) PLL Output Enable—Address 1111010 (0x7A) ALC Control Register 1—Address 1111011 (0x7B) ALC Control Register 2— Address = 1111100 (0x7C) ALC Control Register 3—Address 1111101 (0x7D) LAYOUT CONSIDERATIONS ADC DAC PLL RESET AND POWER-DOWN CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE