Datasheet AD73311 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Low Cost, Low Power CMOS General Purpose Analog Front End |
| Pages / Page | 36 / 7 — AD73311. (AVDD = +5 V. 10%; DVDD = +5 V. 10%; AGND = DGND = 0 V; T. … |
| Revision | B |
| File Format / Size | PDF / 343 Kb |
| Document Language | English |
AD73311. (AVDD = +5 V. 10%; DVDD = +5 V. 10%; AGND = DGND = 0 V; T. TIMING CHARACTERISTICS. A = TMlN to TMAX, unless
Model Line for this Datasheet
Text Version of Document
AD73311 (AVDD = +5 V
ⴞ
10%; DVDD = +5 V
ⴞ
10%; AGND = DGND = 0 V; T TIMING CHARACTERISTICS A = TMlN to TMAX, unless otherwise noted) Limit at Parameter TA = –40
ⴗ
C to +85
ⴗ
C Unit Description
Clock Signals See Figure 1 t1 61 ns min MCLK Period t2 24.4 ns min MCLK Width High t3 24.4 ns min MCLK Width Low Serial Port See Figures 3 and 4 t4 t1 ns min SCLK Period t5 0.4 × t1 ns min SCLK Width High t6 0.4 × t1 ns min SCLK Width Low t7 20 ns typ SDI/SDIFS Setup Before SCLK Low t8 0 ns typ SDI/SDIFS Hold After SCLK Low t9 10 ns typ SDOFS Delay from SCLK High t10 10 ns typ SDOFS Hold After SCLK High t11 10 ns typ SDO Hold After SCLK High t12 10 ns typ SDO Delay from SCLK High t13 30 ns typ SCLK Delay from MCLK
t1 100
A IOL t2 TO OUTPUT +2.1V PIN CL 15pF t3 100
A IOH
Figure 1. MCLK Timing Figure 2. Load Circuit for Timing Specifications
t1 t2 t3 MCLK t13 SCLK* t5 t6 t4 *SCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE).
Figure 3. SCLK Timing REV. B –7–
ⴞ
10%; DVDD = +5 V
ⴞ
10%; AGND = DGND = 0 V; T TIMING CHARACTERISTICS A = TMlN to TMAX, unless otherwise noted) Limit at Parameter TA = –40
ⴗ
C to +85
ⴗ
C Unit Description
Clock Signals See Figure 1 t1 61 ns min MCLK Period t2 24.4 ns min MCLK Width High t3 24.4 ns min MCLK Width Low Serial Port See Figures 3 and 4 t4 t1 ns min SCLK Period t5 0.4 × t1 ns min SCLK Width High t6 0.4 × t1 ns min SCLK Width Low t7 20 ns typ SDI/SDIFS Setup Before SCLK Low t8 0 ns typ SDI/SDIFS Hold After SCLK Low t9 10 ns typ SDOFS Delay from SCLK High t10 10 ns typ SDOFS Hold After SCLK High t11 10 ns typ SDO Hold After SCLK High t12 10 ns typ SDO Delay from SCLK High t13 30 ns typ SCLK Delay from MCLK
t1 100
A IOL t2 TO OUTPUT +2.1V PIN CL 15pF t3 100
A IOH
Figure 1. MCLK Timing Figure 2. Load Circuit for Timing Specifications
t1 t2 t3 MCLK t13 SCLK* t5 t6 t4 *SCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE).
Figure 3. SCLK Timing REV. B –7–
