Datasheet PI6CB33201 (Diodes) - 3
| Manufacturer | Diodes |
| Description | Very-Low-Power Two-Output PCIe Clock Buffer With On-Chip Termination |
| Pages / Page | 20 / 3 — PI6CB33201. Pin Description Cont. Pin Number Pin Name. Type. Description |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
PI6CB33201. Pin Description Cont. Pin Number Pin Name. Type. Description
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A product Line of Diodes Incorporated
PI6CB33201 Pin Description Cont. Pin Number Pin Name Type Description
18 Q1- Output HCSL Differential complementary clock output 19 OE1# Input CMOS Active-low input for enabling Q1 pair. This pin has an internal pulldown. 1 =disable outputs, 0 = enable outputs 20 NC — — Do not connect this pin. 21 VDDO Power — Power supply for differential outputs Input notifies device to sample latched inputs and start up on first high 22 PD# Input CMOS assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has an internal pullup resistor. 23 SADR_TRI Input Tri-level Latch to select SMBus Address. This pin has an internal pulldown. 24 BW_SEL_TRI Input Tri-level Latch to select low-loop bandwidth, bypass PLL, and high-loop band- width. This pin has both internal pullup and pulldown — EPAD Power — Connect to Ground. PI6CB33201 www.diodes.com January 2020 Document Number DS41833 Rev 5-2 3 Diodes Incorporated
PI6CB33201 Pin Description Cont. Pin Number Pin Name Type Description
18 Q1- Output HCSL Differential complementary clock output 19 OE1# Input CMOS Active-low input for enabling Q1 pair. This pin has an internal pulldown. 1 =disable outputs, 0 = enable outputs 20 NC — — Do not connect this pin. 21 VDDO Power — Power supply for differential outputs Input notifies device to sample latched inputs and start up on first high 22 PD# Input CMOS assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has an internal pullup resistor. 23 SADR_TRI Input Tri-level Latch to select SMBus Address. This pin has an internal pulldown. 24 BW_SEL_TRI Input Tri-level Latch to select low-loop bandwidth, bypass PLL, and high-loop band- width. This pin has both internal pullup and pulldown — EPAD Power — Connect to Ground. PI6CB33201 www.diodes.com January 2020 Document Number DS41833 Rev 5-2 3 Diodes Incorporated
