Datasheet PI6CB33201 (Diodes) - 7
| Manufacturer | Diodes |
| Description | Very-Low-Power Two-Output PCIe Clock Buffer With On-Chip Termination |
| Pages / Page | 20 / 7 — PI6CB33201. LVCMOS AC Electrical Characteristics. Symbol. Parameters. … |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
PI6CB33201. LVCMOS AC Electrical Characteristics. Symbol. Parameters. Conditions. Min. Typ. Max. Units. HCSL Input Characteristics(1)
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A product Line of Diodes Incorporated
PI6CB33201 LVCMOS AC Electrical Characteristics
Temperature = TA; Supply voltages per normal operation conditions; See test circuits for the load conditions
Symbol Parameters Conditions Min. Typ. Max. Units
Q start after OE# assertion tOELAT Output Enable Latency 1 — 3 clocks Q stop after OE# de-assertion tPDLAT PD# De-assertion Differential outputs enable after PD# de-assertion — 20 300 µs
HCSL Input Characteristics(1)
Temperature = TA; Supply voltages per normal operation conditions; See test circuits for the load conditions
Symbol Parameters Conditions Min. Typ. Max. Units
VIHDIF Diff. Input High Voltage(3) IN+, IN-, single-end measurement 600 800 1150 mV VILDIF Diff. Input Low Voltage(3) IN+, IN-, single-end measurement -300 0 300 mV V Diff. Input Common Mode COM Voltage 150 900 mV VSWING Diff. Input Swing Voltage Peak to peak value (VIHDIF - VILDIF) 300 2900 mV fINBP Input Frequency PLL Bypass mode 1 200 MHz fIN100 Input Frequency 100MHz PLL 99.9 100 100.1 MHz fIN133 Input Frequency 133MHz PLL 133.2 133.33 133.46 MHz fIN125 Input Frequency 125MHz PLL 124.87 125 125.12 MHz fIN50 Input Frequency 50MHz PLL 49.95 50 50.05 MHz fMODI- Input SS Modulation Freq. Allowable frequency for PCIe applications PCIe PCIe (Triangular Modulation) 30 33 kHz fMODIN- Input SS Modulation Freq. Allowable frequency for non-PCIe applica- non-PCIe non-PCIe tions (Triangular Modulation) 0 46 kHz From VDD Power-Up and after input clock tSTAB Clock stabilization stabilization or de-assertion of PD# to 1st 0.75 1.0 ms clock tRF Diff. Input Slew Rate(2) Measured differentially 0.4 V/ns IIN Diff. Input Leakage Current VIN = VDD, VIN = GND -5 0.01 5 uA tDC Diff. Input Duty Cycle Measured differentially 45 55 % tjc-c Diff. Input Cycle to cycle jitter Measured differentially 125 ps
Note:
1. Guaranteed by design and characterization, not 100% tested in production 2. Slew rate measured through +/-75mV window centered around differential zero 3. The device can be driven by a single-ended clock by driving the true clock and biasing the complement clock input to the Vbias, where Vbias is (VIH-VIL)/2 PI6CB33201 www.diodes.com January 2020 Document Number DS41833 Rev 5-2 7 Diodes Incorporated
PI6CB33201 LVCMOS AC Electrical Characteristics
Temperature = TA; Supply voltages per normal operation conditions; See test circuits for the load conditions
Symbol Parameters Conditions Min. Typ. Max. Units
Q start after OE# assertion tOELAT Output Enable Latency 1 — 3 clocks Q stop after OE# de-assertion tPDLAT PD# De-assertion Differential outputs enable after PD# de-assertion — 20 300 µs
HCSL Input Characteristics(1)
Temperature = TA; Supply voltages per normal operation conditions; See test circuits for the load conditions
Symbol Parameters Conditions Min. Typ. Max. Units
VIHDIF Diff. Input High Voltage(3) IN+, IN-, single-end measurement 600 800 1150 mV VILDIF Diff. Input Low Voltage(3) IN+, IN-, single-end measurement -300 0 300 mV V Diff. Input Common Mode COM Voltage 150 900 mV VSWING Diff. Input Swing Voltage Peak to peak value (VIHDIF - VILDIF) 300 2900 mV fINBP Input Frequency PLL Bypass mode 1 200 MHz fIN100 Input Frequency 100MHz PLL 99.9 100 100.1 MHz fIN133 Input Frequency 133MHz PLL 133.2 133.33 133.46 MHz fIN125 Input Frequency 125MHz PLL 124.87 125 125.12 MHz fIN50 Input Frequency 50MHz PLL 49.95 50 50.05 MHz fMODI- Input SS Modulation Freq. Allowable frequency for PCIe applications PCIe PCIe (Triangular Modulation) 30 33 kHz fMODIN- Input SS Modulation Freq. Allowable frequency for non-PCIe applica- non-PCIe non-PCIe tions (Triangular Modulation) 0 46 kHz From VDD Power-Up and after input clock tSTAB Clock stabilization stabilization or de-assertion of PD# to 1st 0.75 1.0 ms clock tRF Diff. Input Slew Rate(2) Measured differentially 0.4 V/ns IIN Diff. Input Leakage Current VIN = VDD, VIN = GND -5 0.01 5 uA tDC Diff. Input Duty Cycle Measured differentially 45 55 % tjc-c Diff. Input Cycle to cycle jitter Measured differentially 125 ps
Note:
1. Guaranteed by design and characterization, not 100% tested in production 2. Slew rate measured through +/-75mV window centered around differential zero 3. The device can be driven by a single-ended clock by driving the true clock and biasing the complement clock input to the Vbias, where Vbias is (VIH-VIL)/2 PI6CB33201 www.diodes.com January 2020 Document Number DS41833 Rev 5-2 7 Diodes Incorporated
