Preliminary Datasheet EZ-PD CCG6DF, CCG6SF (Cypress) - 8
| Manufacturer | Cypress |
| Description | USB Type-C Port Controller |
| Pages / Page | 50 / 8 — PRELIMINARY. EZ-PD CCG6DF, CCG6SF. Power. Figure 2. CCG6DF Power Supply … |
| File Format / Size | PDF / 1.5 Mb |
| Document Language | English |
PRELIMINARY. EZ-PD CCG6DF, CCG6SF. Power. Figure 2. CCG6DF Power Supply Requirement Block Diagram
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PRELIMINARY EZ-PD CCG6DF, CCG6SF Power
CCG6DF can operate either from VBUS_C (from Port 0 and/or 1) or VSYS supply inputs. In addition, there is V5V supply pin, which sources the VCONN supply to the Type-C connector, the valid levels on V5V supply can range from 4.85 – 5.5 V. V5V does not power the chip. The chip’s internal operating power supply is derived from VSYS (2.75 V to 5.5 V) or VBUS (4 V- 21.5 V). In dead battery mode, the chip can be supplied power from Type-C VBUS (from port 0 and/or 1). In UFP, DFP, and DRP modes (when the system battery is charged), the chip is powered via VSYS. CCG6DF and CCG6SF devices support power modes to minimize energy consumption when not actively involved in data communication over the Type-C port. Figure 2 and Figure 3 show an overview of the power system requirement for CCG6DF and CCG6SF devices. CCG6DF and CCG6SF devices have two different power modes: Active and Deep Sleep, transitions between which are managed by the Power System. A separate power domain, VDDIO, is provided for the GPIOs and VDDD which generates 3.3 V from internal regulator. VDDD can be shorted to VDDIO. VDDD and VCCD are not recommended to be used as power supplies for other circuits on the system. Also, VDDD and VCCD pins cannot be treated as power sources for the chip.The VCCD pin, the output of the core (1.8 V) regulator, is brought out for connecting a 0.1-µF capacitor for the regulator stability only.
Figure 2. CCG6DF Power Supply Requirement Block Diagram
VBUS_C_P0 LDO VDDD VBUS_C_P1 LDO 1µF VSYS CC1_P1 CC2_P1 V5V_P1 CC1_P0 CC2_P0 V5V_P0 Core Regulator VCCD VDDIO 2 x CC GPIOs Core Tx/Rx 0.1µF VSS Document Number: 002-27161 Rev. *E Page 8 of 50 Document Outline EZ-PD CCG6DF, CCG6SF, USB Type-C Port Controller General Description Applications Features USB-PD Type-C Mux Integrated Provider VBUS Load Switch LDO 32-bit MCU Subsystem Integrated Digital Blocks Authentication Clocks and Oscillators Operating Range Hot-Swappable I/Os Packages Logic Block Diagram CCG6DF/CCG6SF Functional Diagram Contents Functional Overview MCU Subsystem CPU Flash, SROM, and RAM USB-PD Subsystem (SS) USB-PD Physical Layer VCONN FET ADC SBU Pass-Through Switch and USB HS Mux Provider Load Switch Undervoltage and Overvoltage Protection on VBUS High-side Current Sense Amplifier for VBUS VBUS Reverse Current Protection VBUS Short Circuit Protection VBUS Discharge VBUS Regulator Gate Driver for VBUS NFET VBUS Tolerant SBU and CC Lines Serial Communication Block (SCB) Timer, Counter, Pulse-Width Modulator (TCPWM) True Random Number Generator (TRNG) GPIO Interface System Resources Watchdog Timer (WDT) Clock System IMO Clock Source ILO Clock Source Power Pinouts Application Diagrams CCG6DF, CCG6SF Layout Design Guidelines for BGA Package Usage of Via Size of 8-mil drill/16-mil diameter and 10-mil drill/16-mil diameter Layer Stack-up Top Layer Fan Out Via Count for GND Pads Via Count for Provider Pads High-Speed (DP_SYS, DM_SYS) USB Connections CC Connections CC lines for CCG6DF/CCG6SF devices carry ~500-mA current. In the top layer, two CC pads are shorted using 0.2mm trace width and connected to other layers through one via. The capacitors are placed on bottom layer and are routed to the Type-C Connecto... Rsense and Capacitor Connections for Provider VBUS The differential signal from Rsense should be length matched. The capacitor for Provider VBUS should be as close as possible to the Rsense and connected using copper shape. Figure 19 and Figure 20 show routing for Rsense. Trace Width Details for Critical Signals VDDIO, VCCD, VSYS, and VDDD Connections Figure 21 and Figure 22 show how the VDDIO, VDDD, VSYS, and VCCD signals get routed amongst the top and bottom layers. Capacitor Connections for CC Lines and Bypass Capacitors for VDDIO, VDDD, VCCD, and VSYS Pins Figure 23 shows how the relevant capacitors can be placed for via sizes of 8-mil drill, 16-mil diameter or 10-mil drill, 16-mil diameter. Electrical Specifications Absolute Maximum Ratings Device-Level Specifications DC Specifications CPU GPIO XRES Digital Peripherals Pulse Width Modulation (PWM) for GPIO Pins I2C UART SPI Memory System Resources Power-on-Reset (POR) with Brown Out SWD Interface Internal Main Oscillator Internal Low-speed Oscillator PD Analog-to-Digital Converter VSYS Switch CSA VBUS UV/OV Provider Side RCP SBU Switch DP/DM Switch VCONN Switch VBUS Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure References and Links to Applications Collateral Knowledge Base Articles Application Notes Reference Designs Kits Datasheets Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support
PRELIMINARY EZ-PD CCG6DF, CCG6SF Power
CCG6DF can operate either from VBUS_C (from Port 0 and/or 1) or VSYS supply inputs. In addition, there is V5V supply pin, which sources the VCONN supply to the Type-C connector, the valid levels on V5V supply can range from 4.85 – 5.5 V. V5V does not power the chip. The chip’s internal operating power supply is derived from VSYS (2.75 V to 5.5 V) or VBUS (4 V- 21.5 V). In dead battery mode, the chip can be supplied power from Type-C VBUS (from port 0 and/or 1). In UFP, DFP, and DRP modes (when the system battery is charged), the chip is powered via VSYS. CCG6DF and CCG6SF devices support power modes to minimize energy consumption when not actively involved in data communication over the Type-C port. Figure 2 and Figure 3 show an overview of the power system requirement for CCG6DF and CCG6SF devices. CCG6DF and CCG6SF devices have two different power modes: Active and Deep Sleep, transitions between which are managed by the Power System. A separate power domain, VDDIO, is provided for the GPIOs and VDDD which generates 3.3 V from internal regulator. VDDD can be shorted to VDDIO. VDDD and VCCD are not recommended to be used as power supplies for other circuits on the system. Also, VDDD and VCCD pins cannot be treated as power sources for the chip.The VCCD pin, the output of the core (1.8 V) regulator, is brought out for connecting a 0.1-µF capacitor for the regulator stability only.
Figure 2. CCG6DF Power Supply Requirement Block Diagram
VBUS_C_P0 LDO VDDD VBUS_C_P1 LDO 1µF VSYS CC1_P1 CC2_P1 V5V_P1 CC1_P0 CC2_P0 V5V_P0 Core Regulator VCCD VDDIO 2 x CC GPIOs Core Tx/Rx 0.1µF VSS Document Number: 002-27161 Rev. *E Page 8 of 50 Document Outline EZ-PD CCG6DF, CCG6SF, USB Type-C Port Controller General Description Applications Features USB-PD Type-C Mux Integrated Provider VBUS Load Switch LDO 32-bit MCU Subsystem Integrated Digital Blocks Authentication Clocks and Oscillators Operating Range Hot-Swappable I/Os Packages Logic Block Diagram CCG6DF/CCG6SF Functional Diagram Contents Functional Overview MCU Subsystem CPU Flash, SROM, and RAM USB-PD Subsystem (SS) USB-PD Physical Layer VCONN FET ADC SBU Pass-Through Switch and USB HS Mux Provider Load Switch Undervoltage and Overvoltage Protection on VBUS High-side Current Sense Amplifier for VBUS VBUS Reverse Current Protection VBUS Short Circuit Protection VBUS Discharge VBUS Regulator Gate Driver for VBUS NFET VBUS Tolerant SBU and CC Lines Serial Communication Block (SCB) Timer, Counter, Pulse-Width Modulator (TCPWM) True Random Number Generator (TRNG) GPIO Interface System Resources Watchdog Timer (WDT) Clock System IMO Clock Source ILO Clock Source Power Pinouts Application Diagrams CCG6DF, CCG6SF Layout Design Guidelines for BGA Package Usage of Via Size of 8-mil drill/16-mil diameter and 10-mil drill/16-mil diameter Layer Stack-up Top Layer Fan Out Via Count for GND Pads Via Count for Provider Pads High-Speed (DP_SYS, DM_SYS) USB Connections CC Connections CC lines for CCG6DF/CCG6SF devices carry ~500-mA current. In the top layer, two CC pads are shorted using 0.2mm trace width and connected to other layers through one via. The capacitors are placed on bottom layer and are routed to the Type-C Connecto... Rsense and Capacitor Connections for Provider VBUS The differential signal from Rsense should be length matched. The capacitor for Provider VBUS should be as close as possible to the Rsense and connected using copper shape. Figure 19 and Figure 20 show routing for Rsense. Trace Width Details for Critical Signals VDDIO, VCCD, VSYS, and VDDD Connections Figure 21 and Figure 22 show how the VDDIO, VDDD, VSYS, and VCCD signals get routed amongst the top and bottom layers. Capacitor Connections for CC Lines and Bypass Capacitors for VDDIO, VDDD, VCCD, and VSYS Pins Figure 23 shows how the relevant capacitors can be placed for via sizes of 8-mil drill, 16-mil diameter or 10-mil drill, 16-mil diameter. Electrical Specifications Absolute Maximum Ratings Device-Level Specifications DC Specifications CPU GPIO XRES Digital Peripherals Pulse Width Modulation (PWM) for GPIO Pins I2C UART SPI Memory System Resources Power-on-Reset (POR) with Brown Out SWD Interface Internal Main Oscillator Internal Low-speed Oscillator PD Analog-to-Digital Converter VSYS Switch CSA VBUS UV/OV Provider Side RCP SBU Switch DP/DM Switch VCONN Switch VBUS Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure References and Links to Applications Collateral Knowledge Base Articles Application Notes Reference Designs Kits Datasheets Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support
