Datasheet LT3952A (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 60V LED Driver with 4A Switch Current |
| Pages / Page | 30 / 10 — PIN FUNCTIONS. GND (1, 12, 28, Exposed Pad Pin 29):. SYNC/SPRD (Pin 11):. … |
| Revision | A |
| File Format / Size | PDF / 2.3 Mb |
| Document Language | English |
PIN FUNCTIONS. GND (1, 12, 28, Exposed Pad Pin 29):. SYNC/SPRD (Pin 11):. SW (Pins 2, 3, 4):. IVINN (Pin 5):. IVINP (Pin 6):
Model Line for this Datasheet
Text Version of Document
link to page 6 link to page 6 LT3952A
PIN FUNCTIONS GND (1, 12, 28, Exposed Pad Pin 29):
Ground Pins. circuitry. Users may apply <5mA loads to INTVCC. Over- The exposed pad of the LT3952A acts as both GND and loading INTVCC can cause unintentional device shutdown heat sink. It must be connected to a large copper area for from INTVCC falling below the 2.68V UVLO threshold. proper operation.
SYNC/SPRD (Pin 11):
Frequency Synchronization and
SW (Pins 2, 3, 4):
Switch Pins. Minimize copper area at Spread Spectrum Enable Pin. Tie low for fixed internal these pins to increase efficiency and reduce EMI. clock, tie to INTVCC for spread spectrum internal clock, or
IVINN (Pin 5):
Input Current Sense Amplifier Negative Input. drive with an external clock for frequency synchronization The input current sense amplifier reduces the switching with no spread spectrum. When using an external clock for current in the case of an overload. VC is reduced when the frequency synchronization, RT resistor should be chosen IVINP-IVINN voltage exceeds the 60mV built-in potential. to program a switching frequency 20% lower than the Tie IVINP-IVINN across an external sense resistor to set SYNC pulse frequency. Synchronization (switch turn-on) auxiliary current limit. If unused, tie to V occurs 50ns after the rising edge of SYNC. IN.
IVINP (Pin 6):
Auxiliary Current Sense Amplifier Posi-
VC (Pin 13):
gm Amplifier Output for External Loop tive Input. Also acts as the bias supply for the amplifier Compensation. Stabilize the loop with a C or series RC to provide a function independent from the V network. This pin is set to a high impedance state during IN pin. The IVINP/IVINN amplifier can operate from voltages either PWM dimming off-time. above or below VIN. Tie this pin to the positive terminal of
RT (Pin 14):
Switching Frequency Adjustment Pin. Set a sense resistor, and do not use resistance in series with switching frequency using a resistor to GND (see Typical this pin. If unused, tie to VIN. Performance Characteristics for values). For SYNC func-
V
tion, set the frequency 20% slower than the SYNC pulse
IN (Pin 7):
Input Supply Pin. Bypass this pin with a ca- pacitor to GND as close to the IC as possible. frequency. Do not leave this pin open. PCB layout must have this component close to the IC.
EN/UVLO (Pin 8):
Master Enable and VIN Undervoltage Lockout. When low, the IC is put into shutdown mode and
DIM (Pin 15):
PWM Generator Control Voltage. This pin the Q current is reduced to <1μA. This pin utilizes a 1.23V outputs a fixed 20μA current, and controls a triangle wave comparator with hysteresis, as well as a hysteresis current generator on the PWM pin to determine the PWM duty source for programming additional hysteresis externally. cycle. 0.2V to 1.2V range on DIM adjusts PWM duty from Drive with a digital signal greater than 1.5V for simple 0% to 100%. Float this pin or tie to INTVCC if unused, tie a on/off control. Tie to a resistor divider between V resistor from DIM to GND to set a fixed voltage, or apply IN and GND to set an external UVLO threshold. an external voltage to DIM for adjustable PWM duty cycle.
OVLO (Pin 9):
Overvoltage Lock Out Comparator. This pin
FB (Pin 16):
Output Voltage Loop Feedback Pin. Connect disables switching and TG in the case of an overvoltage. to a resistor divider from VOUT. In constant-voltage ap- This pin utilizes a 1.23V comparator with hysteresis. When plications, FB sets the output voltage. In constant-current the voltage at OVLO exceeds the threshold, the switching applications, the FB divider is set higher than the expected is disabled until the voltage at OVLO falls 25mV below the output voltage to act as open-LED protection. As the volt- threshold. Tie to GND if unused. age at FB rises to within 45mV of the regulation point, the OPENLED flag is asserted if the output current also
INTVCC (Pin 10):
Internal Low Dropout Regulator Output. falls below one-tenth the full-scale value. If the FB voltage INTVCC is regulated to 3V, and must be bypassed with an exceeds the regulation point by 30mV, the switching is external capacitor of at least 2.2µF. INTVCC is the power terminated and the TG pin pulls high in order to discon- supply for the internal DMOS gate driver and control nect the LED load. Rev A 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS GND (1, 12, 28, Exposed Pad Pin 29):
Ground Pins. circuitry. Users may apply <5mA loads to INTVCC. Over- The exposed pad of the LT3952A acts as both GND and loading INTVCC can cause unintentional device shutdown heat sink. It must be connected to a large copper area for from INTVCC falling below the 2.68V UVLO threshold. proper operation.
SYNC/SPRD (Pin 11):
Frequency Synchronization and
SW (Pins 2, 3, 4):
Switch Pins. Minimize copper area at Spread Spectrum Enable Pin. Tie low for fixed internal these pins to increase efficiency and reduce EMI. clock, tie to INTVCC for spread spectrum internal clock, or
IVINN (Pin 5):
Input Current Sense Amplifier Negative Input. drive with an external clock for frequency synchronization The input current sense amplifier reduces the switching with no spread spectrum. When using an external clock for current in the case of an overload. VC is reduced when the frequency synchronization, RT resistor should be chosen IVINP-IVINN voltage exceeds the 60mV built-in potential. to program a switching frequency 20% lower than the Tie IVINP-IVINN across an external sense resistor to set SYNC pulse frequency. Synchronization (switch turn-on) auxiliary current limit. If unused, tie to V occurs 50ns after the rising edge of SYNC. IN.
IVINP (Pin 6):
Auxiliary Current Sense Amplifier Posi-
VC (Pin 13):
gm Amplifier Output for External Loop tive Input. Also acts as the bias supply for the amplifier Compensation. Stabilize the loop with a C or series RC to provide a function independent from the V network. This pin is set to a high impedance state during IN pin. The IVINP/IVINN amplifier can operate from voltages either PWM dimming off-time. above or below VIN. Tie this pin to the positive terminal of
RT (Pin 14):
Switching Frequency Adjustment Pin. Set a sense resistor, and do not use resistance in series with switching frequency using a resistor to GND (see Typical this pin. If unused, tie to VIN. Performance Characteristics for values). For SYNC func-
V
tion, set the frequency 20% slower than the SYNC pulse
IN (Pin 7):
Input Supply Pin. Bypass this pin with a ca- pacitor to GND as close to the IC as possible. frequency. Do not leave this pin open. PCB layout must have this component close to the IC.
EN/UVLO (Pin 8):
Master Enable and VIN Undervoltage Lockout. When low, the IC is put into shutdown mode and
DIM (Pin 15):
PWM Generator Control Voltage. This pin the Q current is reduced to <1μA. This pin utilizes a 1.23V outputs a fixed 20μA current, and controls a triangle wave comparator with hysteresis, as well as a hysteresis current generator on the PWM pin to determine the PWM duty source for programming additional hysteresis externally. cycle. 0.2V to 1.2V range on DIM adjusts PWM duty from Drive with a digital signal greater than 1.5V for simple 0% to 100%. Float this pin or tie to INTVCC if unused, tie a on/off control. Tie to a resistor divider between V resistor from DIM to GND to set a fixed voltage, or apply IN and GND to set an external UVLO threshold. an external voltage to DIM for adjustable PWM duty cycle.
OVLO (Pin 9):
Overvoltage Lock Out Comparator. This pin
FB (Pin 16):
Output Voltage Loop Feedback Pin. Connect disables switching and TG in the case of an overvoltage. to a resistor divider from VOUT. In constant-voltage ap- This pin utilizes a 1.23V comparator with hysteresis. When plications, FB sets the output voltage. In constant-current the voltage at OVLO exceeds the threshold, the switching applications, the FB divider is set higher than the expected is disabled until the voltage at OVLO falls 25mV below the output voltage to act as open-LED protection. As the volt- threshold. Tie to GND if unused. age at FB rises to within 45mV of the regulation point, the OPENLED flag is asserted if the output current also
INTVCC (Pin 10):
Internal Low Dropout Regulator Output. falls below one-tenth the full-scale value. If the FB voltage INTVCC is regulated to 3V, and must be bypassed with an exceeds the regulation point by 30mV, the switching is external capacitor of at least 2.2µF. INTVCC is the power terminated and the TG pin pulls high in order to discon- supply for the internal DMOS gate driver and control nect the LED load. Rev A 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Package Description Revision History Typical Application Related Parts
