Datasheet LTC6995-1, LTC6995-2 (Analog Devices) - 22
| Manufacturer | Analog Devices |
| Description | TimerBlox: Long Timer, Low Frequency Oscillator |
| Pages / Page | 28 / 22 — APPLICATIONS INFORMATION. DFN PACKAGE. TSOT-23 PACKAGE. Figure 22. Supply … |
| Revision | B |
| File Format / Size | PDF / 1.7 Mb |
| Document Language | English |
APPLICATIONS INFORMATION. DFN PACKAGE. TSOT-23 PACKAGE. Figure 22. Supply Bypassing and PCB Layout
Model Line for this Datasheet
- LTC6995CDCB-1#TRMPBF LTC6995CDCB-1#TRPBF LTC6995CDCB-2#TRMPBF LTC6995CDCB-2#TRPBF LTC6995CS6-1#TRMPBF LTC6995CS6-1#TRPBF LTC6995CS6-2#TRMPBF LTC6995CS6-2#TRPBF LTC6995HDCB-1#TRMPBF LTC6995HDCB-1#TRPBF LTC6995HDCB-2#TRMPBF LTC6995HDCB-2#TRPBF LTC6995HS6-1#TRMPBF LTC6995HS6-1#TRPBF LTC6995HS6-1#WTRMPBF LTC6995HS6-1#WTRPBF LTC6995HS6-2#TRMPBF LTC6995HS6-2#TRPBF LTC6995HS6-2#WTRMPBF LTC6995HS6-2#WTRPBF LTC6995IDCB-1#TRMPBF LTC6995IDCB-1#TRPBF LTC6995IDCB-2#TRMPBF LTC6995IDCB-2#TRPBF LTC6995IS6-1#TRMPBF LTC6995IS6-1#TRPBF LTC6995IS6-1#WTRMPBF LTC6995IS6-1#WTRPBF LTC6995IS6-2#TRMPBF LTC6995IS6-2#TRPBF LTC6995IS6-2#WTRMPBF LTC6995IS6-2#WTRPBF LTC6995MPS6-1#TRMPBF LTC6995MPS6-1#TRPBF LTC6995MPS6-2#TRMPBF LTC6995MPS6-2#TRPBF
Text Version of Document
LTC6995-1/LTC6995-2
APPLICATIONS INFORMATION
RST OUT LTC6995-1 GND V+ V+ C1 0.1µF R1 SET DIV RSET R2 V+ R1 C1 C1 V+ V+ OUT RST OUT DIV GND GND V+ R2 SET RST SET DIV R1 RSET RSET R2 699512 F22
DFN PACKAGE TSOT-23 PACKAGE Figure 22. Supply Bypassing and PCB Layout
2. Place all passive components on the top side of the 4. Connect RSET directly to the GND pin. Using a long path board. This minimizes trace inductance. or vias to the ground plane will not have a significant 3. Place R affect on accuracy, but a direct, short connection is SET as close as possible to the SET pin and make a direct, short connection. The SET pin is a recommended and easy to apply. current summing node and currents injected into this 5. Use a ground trace to shield the SET pin. This provides pin directly modulate the operating frequency. Having another layer of protection from radiated signals. a short connection minimizes the exposure to signal 6. Place R1 and R2 close to the DIV pin. A direct, short pickup. connection to the DIV pin minimizes the external signal coupling. Rev. B 22 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts
APPLICATIONS INFORMATION
RST OUT LTC6995-1 GND V+ V+ C1 0.1µF R1 SET DIV RSET R2 V+ R1 C1 C1 V+ V+ OUT RST OUT DIV GND GND V+ R2 SET RST SET DIV R1 RSET RSET R2 699512 F22
DFN PACKAGE TSOT-23 PACKAGE Figure 22. Supply Bypassing and PCB Layout
2. Place all passive components on the top side of the 4. Connect RSET directly to the GND pin. Using a long path board. This minimizes trace inductance. or vias to the ground plane will not have a significant 3. Place R affect on accuracy, but a direct, short connection is SET as close as possible to the SET pin and make a direct, short connection. The SET pin is a recommended and easy to apply. current summing node and currents injected into this 5. Use a ground trace to shield the SET pin. This provides pin directly modulate the operating frequency. Having another layer of protection from radiated signals. a short connection minimizes the exposure to signal 6. Place R1 and R2 close to the DIV pin. A direct, short pickup. connection to the DIV pin minimizes the external signal coupling. Rev. B 22 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts
