Datasheet LTC6992-1, LTC6992-2, LTC6992-3, LTC6992-4 (Analog Devices) - 22

ManufacturerAnalog Devices
DescriptionTimerBlox: Voltage-Controlled Pulse Width Modulator (PWM)
Pages / Page34 / 22 — APPLICATIONS INFORMATION. ISET Extremes (Master Oscillator Frequency …
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APPLICATIONS INFORMATION. ISET Extremes (Master Oscillator Frequency Extremes)

APPLICATIONS INFORMATION ISET Extremes (Master Oscillator Frequency Extremes)

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APPLICATIONS INFORMATION ISET Extremes (Master Oscillator Frequency Extremes) Pulse Width Modulation Bandwidth and Settling Time
When operating with ISET outside of the recommended The LTC6992 has a wide PWM bandwidth, making it 1.25μA to 20μA range, the master oscillator operates suitable for a variety of feedback applications. Figure 10 outside of the 62.5kHz to 1MHz range in which it is most shows that the frequency response is flat for modulation accurate. frequencies up to nearly 1/10 of the output frequency. The oscillator will still function with reduced accuracy for Beyond that point, some peaking may occur (depending I on NDIV and average duty cycle setting). SET < 1.25µA. At approximately 500nA, the oscillator out- put will be frozen in its current state. The output could halt Duty cycle settling time depends on the master oscillator in a high or low state. This avoids introducing short pulses frequency. Following a ±80mV step change in VMOD, the while frequency modulating a very low frequency output. duty cycle takes approximately eight master clock cycles At the other extreme, it is not recommended to operate (8 • tMASTER) to settle to within 1% of the final value. the master oscillator beyond 2MHz because the accuracy Examples are shown in Figure 11a and Figure 11b. of the DIV pin ADC will suffer. 10 ÷4, 50% 5 ÷16 ÷1, 50% 0 ÷1, 80% –5 )/∆D(0Hz) (dB) ÷4, 15% MOD –10 ∆D(f –15 –200.001 0.01 0.1 1 fMOD/fOUT (Hz/Hz) 6992 F10
Figure 10. PWM Frequency Response
VMOD VMOD 0.1V/DIV 0.1V/DIV OUT OUT 2V/DIV 2V/DIV DUTY CYCLE DUTY CYCLE 5% DIV 5% DIV 10µs/DIV 6992 F11a 10µs/DIV 6992 F11b V+ = 3.3V V+ = 3.3V DIVCODE = 0 DIVCODE = 0 RSET = 200k RSET = 200k VMOD = 0.3V ±40mV VMOD = 0.5V ±40mV
(a) 25% Duty Cycle (b) 50% Duty Cycle Figure 11. PWM Settling Time
Rev. D 22 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
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