Datasheet ISL97801 (Intersil) - 9
| Manufacturer | Intersil |
| Description | High Power LED Driver |
| Pages / Page | 20 / 9 — Pin Descriptions. PIN. NAME. DESCRIPTION |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
Pin Descriptions. PIN. NAME. DESCRIPTION
Model Line for this Datasheet
Text Version of Document
ISL97801
Pin Descriptions PIN NAME DESCRIPTION
1 VDC Internally regulated 5V supply, tracks VIN for input voltages less than 5V. LDO output can also be biased with external supply if VIN is <5.5V. A minimum of 3.3µF decoupling capacitor is needed in this pin. 2 VHI Power FET gate drive supply. Can be biased with external supply if Vin is <5.5V 3 OVP Overvoltage monitor input; tie to VOUT for normal operation 4 SWD1 NMOS power FET drain 5 SWD2 NMOS power FET drain 6 BUCK/BOOSTN Tie to GND for BOOST operation and to VDC for Buck operation 7 LEVEL Sets LED bias current level; VFB(nominal) = VLEVEL/5 8 TEMP Temperature reference, tie to GND to disable temperature compensation 9 FB LED current feedback 10 TMAX Maximum LED temperature set point; if TEMP voltage exceeds TMAX, FB set point will be reduced 11 SWS2 NMOS power FET source 12 SWS1 NMOS power FET source 13 EN/PWM Chip enable and light modulation PWM dimming input 14 MODE Digital Input; tie to GND to set FB reference to 400mV, tie to VDC to control FB reference with LEVEL input 15 ENL LED load isolation MOS gate driver 16 VBAT Input supply monitor 17 NC Leave floating (internally connected) 18 GND Ground return and FB ground reference 19 FAULT Gate drive of fault protection FET. Driven low under fault conditions 20 VIN Input supply FN6428 Rev 1.00 Page 9 of 20 April 2, 2007
Pin Descriptions PIN NAME DESCRIPTION
1 VDC Internally regulated 5V supply, tracks VIN for input voltages less than 5V. LDO output can also be biased with external supply if VIN is <5.5V. A minimum of 3.3µF decoupling capacitor is needed in this pin. 2 VHI Power FET gate drive supply. Can be biased with external supply if Vin is <5.5V 3 OVP Overvoltage monitor input; tie to VOUT for normal operation 4 SWD1 NMOS power FET drain 5 SWD2 NMOS power FET drain 6 BUCK/BOOSTN Tie to GND for BOOST operation and to VDC for Buck operation 7 LEVEL Sets LED bias current level; VFB(nominal) = VLEVEL/5 8 TEMP Temperature reference, tie to GND to disable temperature compensation 9 FB LED current feedback 10 TMAX Maximum LED temperature set point; if TEMP voltage exceeds TMAX, FB set point will be reduced 11 SWS2 NMOS power FET source 12 SWS1 NMOS power FET source 13 EN/PWM Chip enable and light modulation PWM dimming input 14 MODE Digital Input; tie to GND to set FB reference to 400mV, tie to VDC to control FB reference with LEVEL input 15 ENL LED load isolation MOS gate driver 16 VBAT Input supply monitor 17 NC Leave floating (internally connected) 18 GND Ground return and FB ground reference 19 FAULT Gate drive of fault protection FET. Driven low under fault conditions 20 VIN Input supply FN6428 Rev 1.00 Page 9 of 20 April 2, 2007
