Datasheet 8V97003 (IDT) - 2
| Manufacturer | IDT |
| Description | 171.875MHz to 18GHz RF / mmWave Wideband Synthesizer with Integrated VCO |
| Pages / Page | 66 / 2 — Block Diagram. 8V97003 |
| Revision | 20200120 |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
Block Diagram. 8V97003
Model Line for this Datasheet
Text Version of Document
8V97003 Datasheet
Block Diagram 8V97003
Lock LD Detect MULT CPOUT ÷R Charge PFD Pump REF_IN
x2
nREF_IN External Loop Filter 16-bit Int / VTUNE 32-bit Frac Divider SDO SDIO SCLK SPI RF_OUTA CSB nRF_OUTA nRESET /M0 CE Logic and Registers x2 RF_OUTB SYNC nRF_OUTB MUTE ©2020 Renesas Electronics Corporation 2 January 20, 2020 Document Outline Description Typical Applications Features Simplified Block Diagram Block Diagram Contents List of Figures List of Tables Pin Assignments Pin Descriptions Absolute Maximum Ratings Recommended Operating Conditions Thermal Characteristics and Reliability Information DC Electrical Characteristics AC Electrical Characteristics Typical Performance Characteristics Theory of Operation Synthesizer Programming Reference Input Stage Input Reference Divider (R) Reference Doubler Reference Multiplier (MULT) Feedback Divider Phase and Frequency Detector (PFD) and Charge Pump PFD Frequency External Loop Filter Charge Pump High-Impedance Integrated Low Noise VCO Output Clock Distribution and Optional Output Doubler Output Matching Band Selection Disable Phase Adjust RF Output Power Output Phase Synchronization Power-Down Mode Default Power-Up Conditions VCO Calibration 3- or 4-Wire SPI Interface Description 3/4-Wire Mode Active Clock Edge Reset Least Significant Bit Position Addressing Read Operation Mirrored Register Bits Double-Buffered Registers Operation Protocols Register Map Register Block Descriptions Preface Registers Feedback Divider Control Registers Phase Adjustments Control Registers DSM Control Registers Calibration Control Registers Band Select Clock Divider Control Registers Lock Detect Control Registers Power Down Control Registers Input Control Registers Charge Pump Control Registers Re-Sync Control Registers Output Control Registers Status Registers Applications Information Loop Filter Calculations Recommendations for Unused Input and Output Pins Schematic Example Power Considerations Package Outline Drawings Marking Diagram Ordering Information Revision History
Block Diagram 8V97003
Lock LD Detect MULT CPOUT ÷R Charge PFD Pump REF_IN
x2
nREF_IN External Loop Filter 16-bit Int / VTUNE 32-bit Frac Divider SDO SDIO SCLK SPI RF_OUTA CSB nRF_OUTA nRESET /M0 CE Logic and Registers x2 RF_OUTB SYNC nRF_OUTB MUTE ©2020 Renesas Electronics Corporation 2 January 20, 2020 Document Outline Description Typical Applications Features Simplified Block Diagram Block Diagram Contents List of Figures List of Tables Pin Assignments Pin Descriptions Absolute Maximum Ratings Recommended Operating Conditions Thermal Characteristics and Reliability Information DC Electrical Characteristics AC Electrical Characteristics Typical Performance Characteristics Theory of Operation Synthesizer Programming Reference Input Stage Input Reference Divider (R) Reference Doubler Reference Multiplier (MULT) Feedback Divider Phase and Frequency Detector (PFD) and Charge Pump PFD Frequency External Loop Filter Charge Pump High-Impedance Integrated Low Noise VCO Output Clock Distribution and Optional Output Doubler Output Matching Band Selection Disable Phase Adjust RF Output Power Output Phase Synchronization Power-Down Mode Default Power-Up Conditions VCO Calibration 3- or 4-Wire SPI Interface Description 3/4-Wire Mode Active Clock Edge Reset Least Significant Bit Position Addressing Read Operation Mirrored Register Bits Double-Buffered Registers Operation Protocols Register Map Register Block Descriptions Preface Registers Feedback Divider Control Registers Phase Adjustments Control Registers DSM Control Registers Calibration Control Registers Band Select Clock Divider Control Registers Lock Detect Control Registers Power Down Control Registers Input Control Registers Charge Pump Control Registers Re-Sync Control Registers Output Control Registers Status Registers Applications Information Loop Filter Calculations Recommendations for Unused Input and Output Pins Schematic Example Power Considerations Package Outline Drawings Marking Diagram Ordering Information Revision History
