Datasheet KSZ8842-16M, KSZ8842-32M (Microchip) - 7
| Manufacturer | Microchip |
| Description | Two-Port Ethernet Switch with Non-PCI Interface |
| Pages / Page | 132 / 7 — KSZ8842-16M/-32M. TABLE 2-1:. PIN DESCRIPTION FOR KSZ8842-16MQL/MVL … |
| File Format / Size | PDF / 3.0 Mb |
| Document Language | English |
KSZ8842-16M/-32M. TABLE 2-1:. PIN DESCRIPTION FOR KSZ8842-16MQL/MVL (8-/16-BIT). Pin. Pin Name. Type. Description. Number
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KSZ8842-16M/-32M TABLE 2-1: PIN DESCRIPTION FOR KSZ8842-16MQL/MVL (8-/16-BIT) Pin Pin Name Type Description Number
Test Enable 1 TEST_EN I For normal operation, pull-down this pin to ground. Scan Test Scan Mux Enable 2 SCAN_EN I For normal operation, pull-down this pin to ground. Port 1 and Port 2 LED Indicators, defined as follows
Switch Global Control Register 5: SGCR5 bit [15,9] [0, 0] Default [0, 1]
P1LED3/P2LED3 — — P1LED2/P2LED2 Link/Activity 100Link/Activity P1LED1/P2LED1 Full-Duplex/Col 10Link/Activity P1LED0/P2LED0 Speed Full-Duplex
Reg. SGCR5 bit [15,9] [1, 0] [1, 1]
P1LED3/P2LED3 Activity — P1LED2/P2LED2 Link — P1LED1/P2LED1 Full-Duplex/Col — 3 P1LED2 P1LED0/P2LED0 Speed — 4 P1LED1 5 P1LED0
Note:
Link = On; Activity = Blink; Link/Act = On/Blink; Full-Duplex/ OPU 6 P2LED2 Col = On/Blink; Full-Duplex = On (Full-duplex); Off (Half- 7 P2LED1 duplex); Speed = On (100BASE-T); Off (10BASE-T) 8 P2LED0
Note:
P1LED3 is pin 27. P2LED3 is pin 22. Port 1 and Port 2 LED indicators for Repeater mode defined as follows:
Switch Global Control Register 5: SGCR5 bit [15,9] [0,0] Default [0,1] [1,0] [1,1]
P1LED3/P2LED3 RPT_COL, RPT_ACT — RPT_Link3/RX, P1LED2/P2LED2 — RPT_ERR3 RPT_Link2/RX, P1LED1/P2LED1 — RPT_ERR2 RPT_Link1/RX, P1LED0/P2LED0 — RPT_ERR1
Note:
RPT_COL = Blink; RPT_Link3/RX (Host port) = On/Blink; RPT_Link2/RX (Port 2) = On/Blink; RPT_Link1/RX (Port 1) = On/Blink; RPT_ACT = on if any activity, RPT_ERR3/2/1 = RX error on port 3, 2, or 1. 9 DGND GND Digital ground. 3.3V digital V 10 VDDIO P DDIO input power supply for IO with well decoupling capaci- tors. Ready Return Not: For VLBus-like mode: Asserted by the host to complete synchronous 11 RDYRTNN IPD read cycles. If the host doesn’t connect to this pin, assert this pin. For burst mode (32-bit interface only): Host drives this pin low to signal waiting states. 2020 Microchip Technology Inc. DS00003459A-page 7 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Functional Overview: Physical Layer Transceiver 3.2 Functional Overview: MAC and Switch 3.3 Bus Interface Unit (BIU) 3.4 Queue Management Unit (QMU) 3.5 Advanced Switch Functions 3.6 IEEE 802.1Q VLAN Support 3.7 QoS Priority Support 3.8 Rate-Limiting Support 3.9 Loopback Support 4.0 Register Descriptions 4.1 CPU Interface I/O Registers 4.2 Register Map: MAC and PHY 4.3 Type-of-Service (TOS) Priority Control Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Asynchronous Timing without using Address Strobe (ADSN = 0) 7.2 Asynchronous Timing using Address Strobe (ADSN) 7.3 Asynchronous Timing using DATACSN (KSZ8842-32MQL/MVL Only) 7.4 Address Latching Timing for All Modes 7.5 Synchronous Timing in Burst Write (VLBUSN = 1) 7.6 Synchronous Timing in Burst Read (VLBUSN = 1) 7.7 Synchronous Write Timing (VLBUSN = 0) 7.8 Synchronous Read Timing (VLBUSN = 0) 7.9 EEPROM Timing 7.10 Auto-Negotiation Timing 7.11 Reset Timing 8.0 Selection of Isolation Transformers 9.0 Package Outline 9.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
Test Enable 1 TEST_EN I For normal operation, pull-down this pin to ground. Scan Test Scan Mux Enable 2 SCAN_EN I For normal operation, pull-down this pin to ground. Port 1 and Port 2 LED Indicators, defined as follows
Switch Global Control Register 5: SGCR5 bit [15,9] [0, 0] Default [0, 1]
P1LED3/P2LED3 — — P1LED2/P2LED2 Link/Activity 100Link/Activity P1LED1/P2LED1 Full-Duplex/Col 10Link/Activity P1LED0/P2LED0 Speed Full-Duplex
Reg. SGCR5 bit [15,9] [1, 0] [1, 1]
P1LED3/P2LED3 Activity — P1LED2/P2LED2 Link — P1LED1/P2LED1 Full-Duplex/Col — 3 P1LED2 P1LED0/P2LED0 Speed — 4 P1LED1 5 P1LED0
Note:
Link = On; Activity = Blink; Link/Act = On/Blink; Full-Duplex/ OPU 6 P2LED2 Col = On/Blink; Full-Duplex = On (Full-duplex); Off (Half- 7 P2LED1 duplex); Speed = On (100BASE-T); Off (10BASE-T) 8 P2LED0
Note:
P1LED3 is pin 27. P2LED3 is pin 22. Port 1 and Port 2 LED indicators for Repeater mode defined as follows:
Switch Global Control Register 5: SGCR5 bit [15,9] [0,0] Default [0,1] [1,0] [1,1]
P1LED3/P2LED3 RPT_COL, RPT_ACT — RPT_Link3/RX, P1LED2/P2LED2 — RPT_ERR3 RPT_Link2/RX, P1LED1/P2LED1 — RPT_ERR2 RPT_Link1/RX, P1LED0/P2LED0 — RPT_ERR1
Note:
RPT_COL = Blink; RPT_Link3/RX (Host port) = On/Blink; RPT_Link2/RX (Port 2) = On/Blink; RPT_Link1/RX (Port 1) = On/Blink; RPT_ACT = on if any activity, RPT_ERR3/2/1 = RX error on port 3, 2, or 1. 9 DGND GND Digital ground. 3.3V digital V 10 VDDIO P DDIO input power supply for IO with well decoupling capaci- tors. Ready Return Not: For VLBus-like mode: Asserted by the host to complete synchronous 11 RDYRTNN IPD read cycles. If the host doesn’t connect to this pin, assert this pin. For burst mode (32-bit interface only): Host drives this pin low to signal waiting states. 2020 Microchip Technology Inc. DS00003459A-page 7 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Functional Overview: Physical Layer Transceiver 3.2 Functional Overview: MAC and Switch 3.3 Bus Interface Unit (BIU) 3.4 Queue Management Unit (QMU) 3.5 Advanced Switch Functions 3.6 IEEE 802.1Q VLAN Support 3.7 QoS Priority Support 3.8 Rate-Limiting Support 3.9 Loopback Support 4.0 Register Descriptions 4.1 CPU Interface I/O Registers 4.2 Register Map: MAC and PHY 4.3 Type-of-Service (TOS) Priority Control Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Asynchronous Timing without using Address Strobe (ADSN = 0) 7.2 Asynchronous Timing using Address Strobe (ADSN) 7.3 Asynchronous Timing using DATACSN (KSZ8842-32MQL/MVL Only) 7.4 Address Latching Timing for All Modes 7.5 Synchronous Timing in Burst Write (VLBUSN = 1) 7.6 Synchronous Timing in Burst Read (VLBUSN = 1) 7.7 Synchronous Write Timing (VLBUSN = 0) 7.8 Synchronous Read Timing (VLBUSN = 0) 7.9 EEPROM Timing 7.10 Auto-Negotiation Timing 7.11 Reset Timing 8.0 Selection of Isolation Transformers 9.0 Package Outline 9.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
