Datasheet KSZ8852HLE (Microchip)

KSZ8852HLE Two-Port 10/100 Ethernet Switch with 8-/16-Bit Host Interface Features
• IEEE 802.1p/Q Tag Insertion or Removal on a Per-Port Basis (Egress) and Support
Management Capabilities:
Double-Tagging • The KSZ8852 includes all the Functions of a 10/ • VLAN ID Tag/Untag Options on Per Port Basis 100BASE-T/TX Switch System which Combines a • Fully Compliant With IEEE 802.3/802.3u Switch Engine, Frame Buffer Management, Standards Address Look-Up Table, Queue Management, • IEEE 802.3x Full-Duplex with Force Mode Option MIB Counters, Media Access Controllers (MAC) and Half-Duplex Backpressure Collision Flow and PHY Transceivers Control • Non-Blocking Store-and-Forward Switch Fabric • IEEE 802.1w Rapid Spanning Tree Protocol Assures Fast Packet Delivery by Utilizing 1024 Support Entry Forwarding Table • IGMP v1/v2/v3 Snooping for Multicast Packet • Port Mirroring/Monitoring/Sniffing: Ingress and/or Filtering Egress Traffic to Any Port • QoS/CoS Packets Prioritization Support: 802.1p, • MIB Counters for Fully Compliant Statistics DiffServ-Based and Re-Mapping Of 802.1p Gathering-34 Counters Per Port Priority Field Per Port Basis on Four Priority • Loopback Modes for Remote Failure Diagnostics Levels • Rapid Spanning Tree Protocol Support (RSTP) for • IPv4/IPv6 QoS Support Topology Management and Ring/Linear Recovery • IPv6 Multicast Listener Discovery (MLD)
Robust PHY Ports
Snooping Support • Two Integrated IEEE 802.3/802.3u Compliant • Programmable Rate Limiting at the Ingress and Ethernet Transceivers Supporting 10BASE-T and Egress Ports 100BASE-TX • Broadcast Storm Protection • On-Chip Termination Resistors and Internal • 1K Entry Forwarding Table with 32K Frame Buffer Biasing for Differential Pairs to Reduce Power • Four Priority Queues with Dynamic Packet • HP Auto MDI/MDI-X™ Crossover Support Mapping for IEEE 802.1P, IPv4 TOS (DIFFSERV), Eliminating the Need to Differentiate Between IPv6 Traffic Class, Etc. Straight or Crossover Cables in Applications • Source Address Filtering for Implementing Ring
MAC Ports
Topologies • Three Internal Media Access Control (MAC) Units
Comprehensive Configuration Registers Access
• 2Kbyte Jumbo Packet Support • Complete Register Access Via the Parallel Host • Tail Tagging Mode (One Byte Added Before FCS) Interface Support at Port 3 to Inform the Processor which • Facility to Load MAC Address from EEPROM At Ingress Port Receives the Packet and it’s Priority Power Up and Reset Time • Programmable MAC Addresses for Port 1 and • I/O Pin Strapping Facility to Set Certain Register Port 2 and Self-Address Filtering Support Bits from I/O Pins at Reset Time • MAC Filtering Function to Filter or Forward • Control Registers Configurable On-The-Fly Unknown Unicast Packets
Host Interface Advanced Switch Capabilities
• Selectable 8-bit or 16-bit Wide Interface • Non-Blocking Store-and-Forward Switch Fabric • Supports Big- and Little-Endian Processors Assures Fast Packet Delivery By Utilizing 1024 • Indirect Data Bus for Data, Address and Byte Entry Forwarding Table Enable to Access any I/O Registers and RX/TX • IEEE 802.1Q VLAN for Up To 16 Groups with a FIFO Buffers Full Range of VLAN IDs • Large Internal Memory with 12KByte for RX FIFO and 6Kbytes for TX FIFO • Programmable Low, High and Overrun Water  2018 Microchip Technology Inc. DS00002761A-page 1 Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Direction Terminology 3.2 Physical (PHY) Block 3.3 MDI/MDI−X Auto Crossover 3.4 Auto Negotiation 3.5 LINK MD® Cable Diagnostics 3.6 On-Chip Termination Resistors 3.7 Lookback Support 3.8 MAC (Media Access Controller) Block 3.9 Switch Block 3.10 IGMP Support 3.11 IPv6 MLD Snooping 3.12 Port Mirroring Support 3.13 IEEE 802.1Q VLAN Support 3.14 QoS Priority Support 3.15 Rate-Limiting Support 3.16 MAC Address Filtering Function 3.17 Queue Management Unit (QMU) 3.18 Device Clocks 3.19 Power 3.20 Internal Low Voltage LDO Regulator 3.21 Power Management 3.22 Wake-On-LAN 3.23 Interfaces 4.0 Register Descriptions 4.1 Device Registers 4.2 Register Map of CPU Accessible I/O Registers 4.3 Register Bit Definitions 4.4 Type-of-Service (TOS) Priority Control Registers 4.5 Indirect Access Data Registers 4.6 Power Management Control and Wake-Up Event Status 4.7 Go Sleep Time and Clock Tree Power-Down Control Registers 4.8 PHY and MII Basic Control Registers 4.9 Port 1 Control Registers 4.10 Port 2 Control Registers 4.11 Port 3 Control Registers 4.12 Switch Global Control Registers 4.13 Source Address Filtering Registers 4.14 TXQ Rate Control Registers 4.15 Auto-Negotiation Next Page Registers 4.16 EEE and Link Partner Advertisement Registers 4.17 Internal I/O Register Space Mapping for Interrupts, BIU, and Global Reset (0x100 - 0x1FF) 4.18 Host MAC Address Registers: MARL, MARM, and MARH 4.19 Internal I/O Register Space Mapping for the Queue Management Unit (QMU) (0x170 - 0x1FF) 4.20 Internal I/O Register Space Mapping for Interrupt Registers (0x190 - 0x193) 4.21 Internal I/O Register Space Mapping for the Queue Management Unit (QMU) (0x19C - 0x1B9) 4.22 Management Information Base (MIB) Counters 4.23 Static MAC Address Table 4.24 Dynamic MAC Address Table 4.25 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Host Interface Read / Write Timing 7.2 Auto-Negotiation Timing 7.3 Serial EEPROM Interface Timing 7.4 Reset Timing and Power Sequencing 7.5 Reset Circuit Guidelines 7.6 Reference Circuits – LED Strap-In Pins 7.7 Reference Clock – Connection and Selection 8.0 Selection of Isolation Transformers 9.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service