Datasheet KSZ8862-16M, KSZ8862-32M (Microchip) - 8

KSZ8862-16M/-32M TABLE 2-1: SIGNALS (CONTINUED) Pin Pin Name Type Description Number
Local Device Not Active Low output signal, asserted when AEN is Low and A15-A4 17 LDEVN OPD decode to the KSZ8841M address programmed into the high byte of the base address register. LDEVN is a combinational decode of the Address and AEN signal. Read Strobe Not 18 RDN IPD Asynchronous read strobe, active-low. 19 EECS OPU EEPROM Chip Select Asynchronous Ready ARDY may be used when interfacing asynchronous buses to extend bus 20 ARDY OPD access cycles. It is asynchronous to the host CPU or bus clock. this pin need an external 4.7 kΩ pull-up resistor. Cycle Not For VLBus-like mode cycle signal; this pin follows the addressing cycle 21 CYCLEN IPD to signal the command cycle. For burst mode (32-bit interface only), this pin stays High for read cycles and Low for write cycles. Port 2 LED indicator 22 P2LED3 OPD See the description in pins 6, 7, and 8. 23 DGND GND Digital IO ground. 1.2V digital core voltage output (internal 1.2V LDO power supply output), this 1.2V output pin provides power to VDDC, VDDA and VDDAP pins. 24 VDDCO P Note: Internally generated power voltage. Do not connect an external power supply to this pin. This pin is used for connecting external filter (Ferrite bead and capacitors). VLBus-like Mode Pull-down or float: Bus interface is configured for synchronous mode. 25 VLBUSN IPD Pull-up: Bus interface is configured for 8-bit or 16-bit asynchronous mode or EISA-like burst mode. EEPROM Enable 26 EEEN IPD EEPROM is enabled and connected when this pin is pull-up. EEPROM is disabled when this pin is pull-down or no connect. Port 1 LED indicator 27 P1LED3 OPD See the description in pins 3, 4, and 5. EEPROM Data Out 28 EEDO OPD This pin is connected to DI input of the serial EEPROM. EEPROM Serial Clock 29 EESK OPD A 4 μs serial output clock to load configuration data from the serial EEPROM. EEPROM Data In This pin is connected to DO output of the serial EEPROM when EEEN is pull-up. 30 EEDI IPD This pin can be pull-down for 8-bit bus mode, pull-up for 16-bit bus mode or don’t care for 32-bit bus mode when EEEN is pull-down (without EEPROM). Synchronous Write/Read 31 SWR IPD Write/Read signal for synchronous bus accesses. Write cycles when high and Read cycles when low. Address Enable 32 AEN IPU Address qualifier for the address decoding, active-low. DS00003324A-page 8  2020 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Functional Overview: Physical Layer Transceiver 3.2 Functional Overview: MAC and Switch 3.3 Bus Interface Unit (BIU) 3.4 Queue Management Unit (QMU) 3.5 Advanced Switch Functions 3.6 IEEE 802.1Q VLAN Support 3.7 QoS Priority Support 3.8 Rate-Limiting Support 3.9 Loopback Support 4.0 Register Descriptions 4.1 CPU Interface I/O Registers 4.2 Register Map: MAC and PHY 4.3 Type-of-Service (TOS) Priority Control Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Asynchronous Timing without using Address Strobe (ADSN = 0) 7.2 Asynchronous Timing using Address Strobe (ADSN) 7.3 Asynchronous Timing using DATACSN 7.4 Address Latching Timing for All Modes 7.5 Synchronous Timing in Burst Write (VLBUSN = 1) 7.6 Synchronous Timing in Burst Read (VLBUSN = 1) 7.7 Synchronous Write Timing (VLBUSN = 0) 7.8 Synchronous Read Timing (VLBUSN = 0) 7.9 Auto-Negotiation Timing 7.10 Reset Timing 7.11 EEPROM Timing 8.0 Selection of Isolation Transformers 9.0 Package Outline 9.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service