Datasheet LAN9303M, LAN9303Mi (Microchip) - 8

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LAN9303M/LAN9303Mi
2.2.1 SYSTEM CLOCKS/RESET/PME CONTROLLER A clock module generates all the system clocks required by the device. This module interfaces directly with the external 25MHz crystal/oscillator to generate the required clock divisions for each internal module. A 16-bit general purpose timer and 32-bit free-running clock are provided by this module for general purpose use. The Port 1 & 2 PHYs provide general power-down and energy detect power-down modes, which allow a reduction in PHY power consumption. The device reset events are categorized as chip-level resets, multi-module resets, and single-module resets. These reset events are summarized below: • Chip Level Resets - Power-On Reset (Entire chip reset) - nRST Pin Reset (Entire chip reset) • Multi-Module Reset - Digital Reset (All sub-modules except Ethernet PHYs) • Single-Module Resets - Port 2 PHY Reset - Port 1 PHY Reset - Virtual PHY Reset 2.2.2 SYSTEM INTERRUPT CONTROLLER The device provides a multi-tier programmable interrupt structure which is controlled by the System Interrupt Controller. Top level interrupt registers aggregate and control all interrupts from the various sub-modules. The device is capable of generating interrupt events from the following: • Switch Fabric • Ethernet PHYs • GPIOs • General Purpose Timer • Software (general purpose) A dedicated programmable IRQ interrupt output pin is provided for external indication of any device interrupts. The IRQ buffer type, polarity, and de-assertion interval are register configurable. 2.2.3 SWITCH FABRIC The Switch Fabric consists of the following major function blocks: •
10/100 MACs
There is one 10/100 Ethernet MAC per Switch Fabric port, which provides basic 10/100 Ethernet functionality, including transmission deferral, collision back-off/retry, TX/RX FCS checking/generation, TX/RX pause flow con- trol, and transmit back pressure. The 10/100 MACs act as an interface between the Switch Engine and the 10/100 PHYs (for ports 1 and 2) or optional external PHY/MAC on port 1. The port 0 10/100 MAC interfaces the Switch Engine to the external MAC/PHY (see Section 2.3, "Modes of Operation"). Each 10/100 MAC includes RX and TX FIFOs and per port statistic counters. •
Switch Engine
This block, consisting of a 3 port VLAN layer 2 switching engine, provides the control for all forwarding/filtering rules and supports untagged, VLAN tagged, and priority tagged frames. The Switch Engine provides an extensive feature set which includes spanning tree protocol support, multicast packet filtering and Quality of Service (QoS) packet prioritization by VLAN tag, destination address, and port default value or DIFFSERV/TOS, allowing for a range of prioritization implementations. A 512 entry forwarding table provides ample room for MAC address for- warding tables. •
Buffer Manager
This block controls the free buffer space, multi-level transmit queues, transmission scheduling, and packet drop- ping of the Switch Fabric. 32K of buffer RAM allows for the storage of multiple packets while forwarding operations are completed. Each port is allocated a cluster of 4 dynamic QoS queues which allow each queue size to grow and shrink with traffic, effectively utilizing all available memory. This memory is managed dynamically via the Buf- fer Manager block. •
Switch CSRs
This block contains all switch related control and status registers, and allows all aspects of the Switch Fabric to be managed. These registers are indirectly accessible via the system control and status registers. DS00002309A-page 8  2008-2016 Microchip Technology Inc. Document Outline 1.0 Preface 1.1 General Terms 2.0 Introduction 2.1 General Description 2.2 Block Diagram FIGURE 2-1: Internal Block Diagram 2.2.1 System Clocks/Reset/PME Controller 2.2.2 System Interrupt Controller 2.2.3 Switch Fabric 2.2.4 Ethernet PHYs 2.2.5 PHY Management Interface (PMI) 2.2.6 I2C Slave Controller 2.2.7 SMI Slave Controller 2.2.8 EEPROM Controller/Loader 2.2.9 GPIO/LED Controller 2.3 Modes of Operation 2.3.1 Internal PHY Mode 2.3.2 MAC Mode FIGURE 2-2: MII MAC Mode 2.3.3 PHY Mode FIGURE 2-3: MII/RMII PHY Mode 2.3.4 Management Modes TABLE 2-1: Device Modes FIGURE 2-4: Port 0 MAC/PHY Management Modes 3.0 Pin Description and Configuration 3.1 Pin Diagram 3.1.1 72-QFN Pin Diagram FIGURE 3-1: Pin Assignments (TOP VIEW) 3.2 Pin Descriptions TABLE 3-1: LAN Port 1 Pins TABLE 3-2: LAN Port 2 Pins TABLE 3-3: LAN Port 1 & 2 Power and Common Pins TABLE 3-4: Port 1 MII/RMII Pins TABLE 3-5: Port 0 MII/RMII Pins TABLE 3-6: GPIO/LED/Configuration Straps TABLE 3-7: Serial Management/EEPROM Pins TABLE 3-8: Miscellaneous Pins TABLE 3-9: PLL Pins TABLE 3-10: Core and I/O Power and Ground Pins TABLE 3-11: LAN9303M/LAN9303Mi 72-QFN Package Pin Assignments 3.3 Buffer Types TABLE 3-12: Buffer Types 4.0 Clocking, Resets, and Power Management 4.1 Clocks 4.2 Resets TABLE 4-1: Reset Sources and Affected Device Circuitry 4.2.1 Chip-Level Resets 4.2.2 Multi-Module Resets 4.2.3 Single-Module Resets 4.2.4 Configuration Straps TABLE 4-2: Soft-Strap Configuration Strap Definitions TABLE 4-3: Hard-Strap Configuration Strap Definitions TABLE 4-4: PIN/Shared Strap Mapping 4.3 Power Management 4.3.1 Port 1 & 2 PHY Power Management 5.0 System Interrupts 5.1 Functional Overview 5.2 Interrupt Sources FIGURE 5-1: Functional Interrupt Register Hierarchy 5.2.1 Switch Fabric Interrupts 5.2.2 Ethernet PHY Interrupts 5.2.3 GPIO Interrupts 5.2.4 General Purpose Timer Interrupt 5.2.5 Software Interrupt 5.2.6 Device Ready Interrupt 6.0 Switch Fabric 6.1 Functional Overview 6.2 Switch Fabric CSRs 6.2.1 Switch Fabric CSR Writes FIGURE 6-1: Switch Fabric CSR Write Access Flow Diagram 6.2.2 Switch Fabric CSR Reads FIGURE 6-2: Switch Fabric CSR Read Access Flow Diagram 6.2.3 Flow Control Enable Logic TABLE 6-1: Switch Fabric Flow Control Enable Logic 6.3 10/100 Ethernet MACs 6.3.1 Receive MAC 6.3.2 Transmit MAC 6.4 Switch Engine (SWE) 6.4.1 MAC Address Lookup Table FIGURE 6-3: ALR Table Entry Structure 6.4.2 Forwarding Rules 6.4.3 Transmit Priority Queue Selection FIGURE 6-4: Switch Engine Transmit Queue Selection FIGURE 6-5: Switch Engine Transmit Queue Calculation 6.4.4 VLAN Support FIGURE 6-6: VLAN Table Entry Structure 6.4.5 Spanning Tree Support TABLE 6-2: Spanning Tree States 6.4.6 Ingress Flow Metering and Coloring TABLE 6-3: Typical Ingress Rate Settings FIGURE 6-7: Switch Engine Ingress Flow Priority Selection FIGURE 6-8: Switch Engine Ingress Flow Priority Calculation 6.4.7 Broadcast Storm Control TABLE 6-4: Typical Broadcast Rate Settings 6.4.8 IPv4 IGMP Support 6.4.9 Port Mirroring 6.4.10 Host CPU Port Special Tagging 6.4.11 Counters 6.5 Buffer Manager (BM) 6.5.1 Packet Buffer Allocation 6.5.2 Random Early Discard (RED) 6.5.3 Transmit Queues 6.5.4 Transmit Priority Queue Servicing 6.5.5 Egress Rate Limiting (Leaky Bucket) TABLE 6-5: Typical Egress Rate Settings 6.5.6 Adding, Removing, and Changing VLAN Tags FIGURE 6-9: Hybrid Port Tagging and Un-tagging 6.5.7 Counters 6.6 Switch Fabric Interrupts 7.0 Ethernet PHYs 7.1 Functional Overview 7.1.1 PHY Addressing TABLE 7-1: Default PHY Serial MII Addressing 7.2 Port 1 & 2 PHYs FIGURE 7-1: Port x PHY Block Diagram 7.2.1 100BASE-TX Transmit FIGURE 7-2: 100BASE-TX Transmit Data Path TABLE 7-2: 4B/5B Code Table 7.2.2 100BASE-TX Receive FIGURE 7-3: 100BASE-TX Receive Data Path 7.2.3 10BASE-T Transmit 7.2.4 10BASE-T Receive 7.2.5 PHY Auto-negotiation 7.2.6 HP Auto-MDIX FIGURE 7-4: Direct Cable Connection vs. Cross-Over Cable Connection 7.2.7 MII MAC Interface 7.2.8 PHY Management Control TABLE 7-3: PHY Interrupt Sources 7.2.9 PHY Power-Down Modes 7.2.10 PHY Resets 7.2.11 LEDs 7.2.12 Required Ethernet Magnetics 7.3 Virtual PHY 7.3.1 Virtual PHY Auto-Negotiation 7.3.2 Virtual PHY in MAC Mode 7.3.3 Virtual PHY Resets 8.0 Serial Management 8.1 Functional Overview 8.2 I2C Overview FIGURE 8-1: I2C Cycle 8.3 I2C Master EEPROM Controller TABLE 8-1: I2C EEPROM Size Ranges 8.3.1 I2C EEPROM Device Addressing FIGURE 8-2: I2C EEPROM Addressing 8.3.2 I2C EEPROM Byte Read FIGURE 8-3: I2C EEPROM Byte Read 8.3.3 I2C EEPROM Sequential Byte Reads FIGURE 8-4: I2C EEPROM Sequential Byte Reads 8.3.4 I2C EEPROM Byte Writes FIGURE 8-5: I2C EEPROM Byte Write 8.3.5 Wait State Generation 8.3.6 I2C Bus Arbitration and Clock Synchronization 8.3.7 I2C Master EEPROM Controller Operation FIGURE 8-6: EEPROM Access Flow Diagram 8.4 EEPROM Loader TABLE 8-2: EEPROM Contents Format Overview 8.4.1 EEPROM Loader Operation FIGURE 8-7: EEPROM Loader Flow Diagram 8.4.2 EEPROM Valid Flag 8.4.3 MAC Address 8.4.4 Soft-Straps TABLE 8-3: EEPROM Configuration Bits 8.4.5 Register Data 8.4.6 EEPROM Loader Finished Wait-State 8.4.7 Reset Sequence and EEPROM Loader 8.5 I2C Slave Operation 8.5.1 I2C Slave Command Format FIGURE 8-8: I2C Slave Addressing 8.5.2 I2C Slave Read Sequence FIGURE 8-9: I2C Slave Reads 8.5.3 I2C Slave Write Sequence FIGURE 8-10: I2C Slave Writes 9.0 MII Data Interfaces 9.1 Port 0 MII Data Path 9.1.1 Port 0 MII MAC Mode 9.1.2 Port 0 MII PHY Mode 9.1.3 Port 0 RMII PHY Mode 9.2 Port 1 MII MUX/Data Path 9.2.1 Port 1 Internal Mode 9.2.2 Port 1 MII MAC Mode 9.2.3 Port 1 MII PHY Mode 9.2.4 Port 1 RMII PHY Mode 10.0 MII Management 10.1 Functional Overview 10.2 SMI Slave Controller TABLE 10-1: SMI Frame Format 10.2.1 Read Sequence 10.2.2 Write Sequence 10.3 PHY Management Interface (PMI) TABLE 10-2: MII Management Frame Format 10.3.1 EEPROM Loader PHY Register Access 10.4 MII Mode Multiplexer 10.4.1 Port 0 MAC Mode SMI Managed FIGURE 10-1: MII Mux Management Path Connections - MAC Mode SMI Managed 10.4.2 Port 0 MAC Mode I2C Managed FIGURE 10-2: MII Mux Management Path Connections - MAC Mode I2C Managed 10.4.3 Port 0 PHY Mode SMI Managed FIGURE 10-3: MII Mux Management Path Connections - PHY Mode SMI Managed 10.4.4 Port 0 PHY Mode I2C Managed FIGURE 10-4: MII Mux Management Path Connections - PHY Mode I2C Managed 11.0 General Purpose Timer & Free-Running Clock 11.1 General Purpose Timer 11.2 Free-Running Clock 12.0 GPIO/LED Controller 12.1 Functional Overview 12.2 GPIO Operation 12.2.1 GPIO Interrupts 12.3 LED Operation TABLE 12-1: LED Operation as a Function of LED_FUN[1:0] 12.3.1 The various LED indication functions shown in Table 12-1 are described in the following sections.LED Function Definitions when LED_FUN[1:0] = 00b, 01b, or 10b 12.3.2 LED Function Definitions when LED_FUN[1:0] = 11b 13.0 Register Descriptions FIGURE 13-1: Base Register Memory Map 13.1 Register Nomenclature TABLE 13-1: Register Bit Types 13.2 System Control and Status Registers TABLE 13-2: System Control and Status Registers 13.2.1 Interrupts 13.2.2 GPIO/LED 13.2.3 EEPROM 13.2.4 Switch Fabric TABLE 13-3: SWITCH_MAC_ADDRL, SWITCH_MAC_ADDRH, and EEPROM Byte Ordering FIGURE 13-2: Example SWITCH_MAC_ADDRL, SWITCH_MAC_ADDRH, and EEPROM Setup TABLE 13-4: Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map 13.2.5 PHY Management Interface (PMI) 13.2.6 Virtual PHY TABLE 13-5: Virtual PHY MII Serially Adressable Register Index TABLE 13-6: Emulated Link Partner Pause Flow Control Ability Default Values TABLE 13-7: Emulated Link Partner Default Advertised Ability 13.2.7 Miscellaneous 13.3 Ethernet PHY Control and Status Registers 13.3.1 Virtual PHY Registers 13.3.2 Port 1 & 2 PHY Registers TABLE 13-8: Port 1 & 2 PHY MII Serially Adressable Registers TABLE 13-9: 10BASE-T Full Duplex Advertisement Default Value TABLE 13-10: 10BASE-T Half Duplex Advertisement Bit Default Value TABLE 13-11: MODE[2:0] Definitions TABLE 13-12: Auto-MDIX Enable and Auto-MDIX State Bit Functionality TABLE 13-13: MDIX Strap Functionality 13.4 Switch Fabric Control and Status Registers TABLE 13-14: Indirectly Accessible Switch Control and Status Registers 13.4.1 General Switch CSRs 13.4.2 Switch Port 0, Port 1, and Port 2 CSRs 13.4.3 Switch Engine CSRs TABLE 13-15: Metering/Color Table Register Descriptions 13.4.4 Buffer Manager CSRs 14.0 Operational Characteristics 14.1 Absolute Maximum Ratings* 14.2 Operating Conditions** 14.3 Power Consumption TABLE 14-1: Supply and Current (10BASE-T Full-Duplex) TABLE 14-2: Supply and Current (100BASE-TX Full-Duplex) TABLE 14-3: Supply and Current (Power Management) 14.4 DC Specifications TABLE 14-4: I/O Buffer Characteristics TABLE 14-5: 100BASE-TX Transceiver Characteristics TABLE 14-6: 10BASE-T Transceiver Characteristics 14.5 AC Specifications 14.5.1 Equivalent Test Load FIGURE 14-1: Output Equivalent Test Load 14.5.2 Reset and Configuration Strap Timing FIGURE 14-2: nRST Reset Pin Timing TABLE 14-7: nRST Reset Pin Timing Values 14.5.3 Power-On Configuration Strap Valid Timing FIGURE 14-3: Power-On Configuration Strap Latching Timing FIGURE 14-4: Power-On Configuration Strap Latching Timing Values 14.5.4 MII Interface Timing (MAC Mode) FIGURE 14-5: MII Output Timing (MAC Mode) TABLE 14-8: MII Output Timing Values (MAC Mode) FIGURE 14-6: MII Input Timing (MAC Mode) TABLE 14-9: MII Input Timing Values (MAC Mode) 14.5.5 MII Interface Timing (PHY Mode) FIGURE 14-7: MII Output Timing (PHY Mode) TABLE 14-10: MII Output Timing Values (PHY Mode) FIGURE 14-8: MII Input Timing (PHY Mode) TABLE 14-11: MII Input Timing Values (PHY Mode) 14.5.6 Turbo MII Interface Timing (MAC Mode) FIGURE 14-9: Turbo MII Output Timing (MAC Mode) TABLE 14-12: Turbo MII Output Timing Values (MAC Mode) FIGURE 14-10: Turbo MII Input Timing (MAC Mode) TABLE 14-13: Turbo MII Input Timing Values (MAC Mode) 14.5.7 Turbo MII Interface Timing (PHY Mode) FIGURE 14-11: Turbo MII Output Timing (PHY Mode) TABLE 14-14: Turbo MII Output Timing Values (PHY Mode) FIGURE 14-12: Turbo MII Input Timing (PHY Mode) TABLE 14-15: Turbo MII Input Timing Values (PHY Mode) 14.5.8 RMII Interface Timing FIGURE 14-13: RMII Px_OUTCLK Output Mode Timing TABLE 14-16: RMII Px_OUTCLK Output Mode Timing Values FIGURE 14-14: RMII Px_OUTCLK Input Mode Timing TABLE 14-17: RMII Px_OUTCLK Input Mode Timing Values 14.5.9 SMI Timing FIGURE 14-15: SMI Timing TABLE 14-18: SMI Timing Values 14.6 Clock Circuit TABLE 14-19: Crystal Specifications 15.0 Package Outlines 15.1 72-QFN Package Outline FIGURE 15-1: 72-QFN Package Definition, 10x10mm Body, 0.5mm Pitch Appendix A: Data sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service