Datasheet VSC7415 (Microchip) - 10
| Manufacturer | Microchip |
| Description | 6-Port SGMII Gigabit Ethernet Switch with VeriTime and Integrated DPLL and Gigabit Ethernet PHYs |
| Pages / Page | 444 / 10 — Figures |
| File Format / Size | PDF / 6.2 Mb |
| Document Language | English |
Figures
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Figures
Figure 1 Wireless Backhaul Application . 6 Figure 2 4G/LTE Small Cell Application . 7 Figure 3 RTL Block Diagram . 10 Figure 4 Block Diagram . 11 Figure 5 Default Scheduler-Shaper Configuration . 15 Figure 6 Frame with Internal Frame Header . 18 Figure 7 Internal Frame Header . 19 Figure 8 Frame With VStaX Header . 24 Figure 9 VStaX Header Layout . 25 Figure 10 Register Space Layout . 31 Figure 11 Cat5 Media Interface . 32 Figure 12 Low Power Idle Operation . 33 Figure 13 Wake-On-LAN Functionality . 34 Figure 14 Inline Powered Ethernet Switch . 35 Figure 15 ActiPHY State Diagram . 36 Figure 16 Far-End Loopback Diagram . 38 Figure 17 Near-End Loopback Diagram . 38 Figure 18 Connector Loopback Diagram . 38 Figure 19 Frame Injection Formats . 46 Figure 20 VCAP Cache Layout Example . 50 Figure 21 VCAP Cache Type-Group Example . 53 Figure 22 Processing Flow . 62 Figure 23 VLAN Acceptance Filter . 101 Figure 24 Basic QoS Classification Flow Chart . 103 Figure 25 Basic DP Classification Flow Chart . 104 Figure 26 Basic DSCP Classification Flow Chart . 105 Figure 27 Basic VLAN Classification Flow Chart . 107 Figure 28 Example of QoS Mappings . 119 Figure 29 VLAN Table Update Engine (TUPE) . 125 Figure 30 Router Model . 131 Figure 31 Unicast Routing Table Overview . 132 Figure 32 Multicast Routing Table Overview . 133 Figure 33 Ingress Router Leg Lookup Flow . 134 Figure 34 Ingress Router Leg MAC Address Matching for Unicast Packets . 134 Figure 35 IP Unicast Routing Example . 137 Figure 36 ARP Pointer Remapping . 139 Figure 37 IP Multicast Routing Example . 141 Figure 38 MAC Table Organization . 166 Figure 39 DMAC Lookup . 174 Figure 40 Source Check . 176 Figure 41 PGID Layout . 181 Figure 42 PGID Lookup Decision Forwarding . 182 Figure 43 GLAG Port of Exit Calculation . 184 Figure 44 Port Mask Operation . 185 Figure 45 Policer Hierarchy . 187 Figure 46 Sticky Events Available as Global Events . 195 Figure 47 Port Statistics Counters . 195 Figure 48 Queue Statistics . 197 Figure 49 BUM Policer Statistics . 198 Figure 50 ACL Policer Statistics . 199 Figure 51 Ingress and Egress Routing Statistics per Router Leg per IP Version . 200 Figure 52 sFlow Stamp Format in FCS . 202 Figure 53 Ingress Mirroring in Specific VLAN . 204 Figure 54 Shared Queue System Block Diagram . 205 VMDS-10447 VSC7415 Datasheet Revision 4.1 x Document Outline 1 Revision History 1.1 Revision 4.1 1.2 Revision 4.0 2 Product Overview 2.1 General Features 2.1.1 Layer 2 and Layer 3 Forwarding 2.1.2 Timing and Synchronization 2.1.3 Quality of Service 2.1.4 Security 2.1.5 Management 2.1.6 Product Parameters 2.2 Applications 2.2.1 Wireless Backhaul 2.2.2 Small Cell Application 3 Functional Descriptions 3.1 Register Notations 3.2 Functional Overview 3.2.1 Frame Arrival in Ports and Port Modules 3.2.2 Basic Classification 3.2.3 Security and Control Protocol Classification 3.2.4 Policing 3.2.5 Layer 2 Forwarding 3.2.6 Layer 3 Forwarding 3.2.7 Shared Queue System and Hierarchical Scheduler 3.2.8 Rewriter and Frame Departure 3.2.9 CPU Port Module 3.2.10 Synchronous Ethernet and Precision Time Protocol (PTP) 3.2.11 CPU Subsystem 3.3 Frame Headers 3.3.1 Internal Frame Header Placement 3.3.2 Internal Frame Header Layout 3.3.3 VStaX Header 3.4 Port Numbering and Mappings 3.4.1 Supported SerDes Interfaces 3.4.2 Dual-Media Mode 3.4.3 Logical Port Numbers 3.5 SERDES1G 3.6 SERDES6G 3.7 Copper Transceivers 3.7.1 Register Access 3.7.2 Cat5 Twisted Pair Media Interface 3.7.3 Wake-On-LAN and SecureOn 3.7.4 Ethernet Inline Powered Devices 3.7.5 IEEE 802.3af PoE Support 3.7.6 ActiPHY™ Power Management 3.7.7 Testing Features 3.7.8 VeriPHY™ Cable Diagnostics 3.8 DEV1G and DEV2G5 Port Modules 3.8.1 MAC 3.8.2 Half-Duplex Mode 3.8.3 Physical Coding Sublayer (PCS) 3.8.4 Port Statistics 3.9 Assembler 3.9.1 Setting Up a Port in the Assembler 3.9.2 Setting Up a Port for Frame Injection 3.9.3 Setting Up MAC Control Sublayer PAUSE Frame Detection 3.9.4 Setting Up PFC 3.9.5 Setting Up Assembler Port Statistics 3.9.6 Setting Up the Loopback Path 3.10 Versatile Content-Aware Processor (VCAP) 3.10.1 Configuring VCAP 3.10.2 Wide VCAP Entries and Actions 3.10.3 Individual VCAPs 3.10.4 VCAP Programming Examples 3.11 Pipeline Points 3.11.1 Pipeline Definitions 3.12 Analyzer 3.12.1 Initializing the Analyzer 3.13 VCAP CLM Keys and Actions 3.13.1 Keys Overview 3.13.2 VCAP CLM X1 Key Details 3.13.3 VCAP CLM X2 Key Details 3.13.4 VCAP CLM X4 Key Details 3.13.5 VCAP CLM X8 Key Details 3.13.6 VCAP CLM X16 Key Details 3.13.7 VCAP CLM Actions 3.14 Analyzer Classifier 3.14.1 Basic Classifier 3.14.2 VCAP CLM Processing 3.14.3 QoS Mapping Table 3.14.4 Analyzer Classifier Diagnostics 3.15 VLAN and MSTP 3.15.1 Private VLAN 3.15.2 VLAN Pseudo Code 3.16 VCAP LPM: Keys and Action 3.16.1 VCAP LPM SGL_IP4 Key Details 3.16.2 VCAP LPM DBL_IP4 Key Details 3.16.3 VCAP LPM SGL_IP6 Key Details 3.16.4 VCAP LPM DBL_IP6 Key Details 3.16.5 VCAP LPM Actions 3.17 IP Processing 3.17.1 IP Source/Destination Guard 3.17.2 IP Routing 3.17.3 Statistics 3.17.4 IGMP/MLD Snooping Switch 3.18 VCAP IS2 Keys and Actions 3.18.1 VCAP IS2 Keys 3.18.2 VCAP IS2 Actions 3.19 Analyzer Access Control Lists 3.19.1 VCAP IS2 3.19.2 Analyzer Access Control List Frame Rewriting 3.20 Analyzer Layer 2 Forwarding and Learning 3.20.1 Analyzer MAC Table 3.20.2 MAC Table Updates 3.20.3 CPU Access to MAC Table 3.20.4 SCAN Command 3.20.5 Forwarding Lookups 3.20.6 Source Check and Automated Learning 3.20.7 Automated Aging (AUTOAGE) 3.20.8 Interrupt Handling 3.21 Analyzer Access Control Forwarding, Policing, and Statistics 3.21.1 Mask Handling 3.21.2 Policing 3.21.3 Analyzer Statistics 3.21.4 Analyzer sFlow Sampling 3.21.5 Mirroring 3.22 Shared Queue System and Hierarchical Scheduler 3.22.1 Analyzer Result 3.22.2 Buffer Control 3.22.3 Forwarding 3.22.4 Congestion Control 3.22.5 Queue Mapping 3.22.6 Queue Congestion Control 3.22.7 Scheduling 3.22.8 Queue System Initialization 3.22.9 Miscellaneous Features 3.23 Automatic Frame Injector 3.23.1 Injection Tables 3.23.2 Frame Table 3.23.3 Delay Triggered Injection 3.23.4 Timer Triggered Injection 3.23.5 Injection Queues 3.23.6 Adding Injection Frame 3.23.7 Starting Injection 3.23.8 Stopping Injection 3.23.9 Removing Injection Frames 3.23.10 Port Parameters 3.24 Rewriter 3.24.1 Rewriter Operation 3.24.2 Supported Ports 3.24.3 Supported Frame Formats 3.24.4 Rewriter Initialization 3.24.5 VCAP_ES0 Lookup 3.24.6 Mapping Tables 3.24.7 VLAN Editing 3.24.8 DSCP Remarking 3.24.9 VStaX Header Insertion 3.24.10 Forwarding to GCPU 3.24.11 Layer 3 Routing 3.24.12 Mirror Frames 3.24.13 Internal Frame Header Insertion 3.24.14 Frame Injection from Internal CPU 3.25 Disassembler 3.25.1 Setting Up Ports 3.25.2 Maintaining the Cell Buffer 3.25.3 Setting Up MAC Control Sublayer PAUSE Function 3.25.4 Setting up Flow Control in Half-Duplex Mode 3.25.5 Setting Up Frame Aging 3.25.6 Setting Up Transmit Data Rate Limiting 3.25.7 Error Detection 3.26 Layer 1 Timing 3.27 Hardware Time Stamping 3.27.1 One-Step Functions 3.27.2 Calculation Overview 3.27.3 Detecting Calculation Issues 3.27.4 Two-Step Functions 3.27.5 Time of Day Time Stamping 3.27.6 Time of Day Generation 3.27.7 Multiple PTP Time Domains 3.27.8 Register Interface to 1588 Functions 3.27.9 Configuring I/O Delays 3.28 SyncE and PTP DPLL Timing 3.28.1 Input Clock Selection 3.29 EEC/PEC Controller 3.29.1 Input Qualification Timers 3.29.2 Reference Clock Selection 3.29.3 Output Clock Synthesizers 3.29.4 Synchronizing IEEE 1588 Time Stamping 3.29.5 I/O Pin Mapping 3.30 VRAP Engine 3.30.1 VRAP Request Frame Format 3.30.2 VRAP Response Frame Format 3.30.3 VRAP Header Format 3.30.4 VRAP READ Command 3.30.5 VRAP READ-MODIFY-WRITE Command 3.30.6 VRAP IDLE Command 3.30.7 VRAP PAUSE Command 3.31 Energy Efficient Ethernet 3.32 CPU Injection and Extraction 3.32.1 Frame Injection 3.32.2 Frame Extraction 3.32.3 Forwarding to CPU 3.32.4 Automatic Frame Injection (AFI) 3.33 Priority-Based Flow Control (PFC) 3.33.1 PFC Pause Frame Generation 3.33.2 PFC Frame Reception 3.34 Protection Switching 3.34.1 Ethernet Ring Protection Switching 3.34.2 Link Aggregation 3.34.3 Port Protection Switching 3.35 Low Power Mode 3.35.1 One-Time Configurations for Low Power Mode 3.35.2 General Considerations in Low Power Mode 3.36 Clocking and Reset 3.36.1 Pin Strapping 4 VCore-III System and CPU Interfaces 4.1 VCore-III Configurations 4.2 Clocking and Reset 4.2.1 Watchdog Timer 4.3 Shared Bus 4.3.1 VCore-III Shared Bus Arbitration 4.3.2 Chip Register Region 4.3.3 SI Flash Region 4.3.4 DDR3/DDR3L Region 4.3.5 PCIe Region 4.4 VCore-III CPU 4.4.1 Little Endian and Big Endian Support 4.4.2 Software Debug and Development 4.5 External CPU Support 4.5.1 Register Access and Multimaster Systems 4.5.2 Serial Interface in Slave Mode 4.5.3 MIIM Interface in Slave Mode 4.5.4 Access to the VCore Shared Bus 4.5.5 Mailbox and Semaphores 4.6 PCIe Endpoint Controller 4.6.1 Accessing Endpoint Registers 4.6.2 Enabling the Endpoint 4.6.3 Base Address Registers Inbound Requests 4.6.4 Outbound Interrupts 4.6.5 Outbound Access 4.6.6 Power Management 4.6.7 Device Reset Using PCIe 4.7 Frame DMA 4.7.1 DMA Control Block Structures 4.7.2 Enabling and Disabling FDMA Channels 4.7.3 Channel Counters 4.7.4 FDMA Events and Interrupts 4.7.5 FDMA Extraction 4.7.6 FDMA Injection 4.7.7 Manual Mode 4.8 VCore-III System Peripherals 4.8.1 SI Boot Controller 4.8.2 SI Master Controller 4.8.3 DDR3/DDR3L Memory Controller 4.8.4 Timers 4.8.5 UARTs 4.8.6 Two-Wire Serial Interface 4.8.7 MII Management Controller 4.8.8 GPIO Controller 4.8.9 Serial GPIO Controller 4.8.10 Fan Controller 4.8.11 Temperature Sensor 4.8.12 Memory Integrity Monitor 4.8.13 Interrupt Controller 5 Registers 6 Electrical Specifications 6.1 DC Characteristics 6.1.1 Reference Clock 6.1.2 PLL Clock Output 6.1.3 DPLL Clocks 6.1.4 DDR3/DDR3L SDRAM Interface 6.1.5 SERDES1G 6.1.6 SERDES6G 6.1.7 GPIO, SI, JTAG, and Miscellaneous Signals 6.1.8 Thermal Diode 6.2 AC Characteristics 6.2.1 Reference Clock 6.2.2 PLL Clock Outputs 6.2.3 DPLL Clocks 6.2.4 Jitter Transfer 6.2.5 SERDES1G 6.2.6 SERDES6G 6.2.7 Reset Timing 6.2.8 MII Management 6.2.9 Serial Interface (SI) Boot Master Mode 6.2.10 Serial Interface (SI) Master Mode 6.2.11 Serial Interface (SI) for Slave Mode 6.2.12 DDR SDRAM Interface 6.2.13 JTAG Interface 6.2.14 Serial Inputs/Outputs 6.2.15 Recovered Clock Outputs 6.2.16 Two-Wire Serial Interface 6.2.17 IEEE 1588 Time Tick Outputs 6.3 Current and Power Consumption 6.3.1 Current Consumption 6.3.2 Power Consumption 6.3.3 Power Supply Sequencing 6.4 Operating Conditions 6.5 Stress Ratings 7 Pin Descriptions 7.1 Pin Diagram 7.2 Pins by Function 7.2.1 DDR SDRAM Interface 7.2.2 DPLL Clock 7.2.3 General-Purpose Inputs and Outputs 7.2.4 JTAG Interface 7.2.5 MII Management Interface 7.2.6 Miscellaneous 7.2.7 PCI Express Interface 7.2.8 Power Supplies and Ground 7.2.9 SERDES1G 7.2.10 SERDES6G 7.2.11 Serial CPU Interface 7.2.12 System Clock Interface 7.2.13 Twisted Pair Interface 7.3 Pins by Number 7.4 Pins by Name 8 Package Information 8.1 Package Drawing 8.2 Thermal Specifications 8.3 Moisture Sensitivity 9 Design Guidelines 9.1 Power Supplies 9.2 Power Supply Decoupling 9.2.1 Reference Clock 9.2.2 Single-Ended REFCLK Input 9.3 Interfaces 9.3.1 General Recommendations 9.3.2 SerDes Interfaces (SGMII, 2.5G) 9.3.3 Serial Interface 9.3.4 PCI Express Interface 9.3.5 Two-Wire Serial Interface 9.3.6 DDR3 SDRAM Interface 9.3.7 Thermal Diode External Connection 10 Design Considerations 11 Ordering Information
Figures
Figure 1 Wireless Backhaul Application . 6 Figure 2 4G/LTE Small Cell Application . 7 Figure 3 RTL Block Diagram . 10 Figure 4 Block Diagram . 11 Figure 5 Default Scheduler-Shaper Configuration . 15 Figure 6 Frame with Internal Frame Header . 18 Figure 7 Internal Frame Header . 19 Figure 8 Frame With VStaX Header . 24 Figure 9 VStaX Header Layout . 25 Figure 10 Register Space Layout . 31 Figure 11 Cat5 Media Interface . 32 Figure 12 Low Power Idle Operation . 33 Figure 13 Wake-On-LAN Functionality . 34 Figure 14 Inline Powered Ethernet Switch . 35 Figure 15 ActiPHY State Diagram . 36 Figure 16 Far-End Loopback Diagram . 38 Figure 17 Near-End Loopback Diagram . 38 Figure 18 Connector Loopback Diagram . 38 Figure 19 Frame Injection Formats . 46 Figure 20 VCAP Cache Layout Example . 50 Figure 21 VCAP Cache Type-Group Example . 53 Figure 22 Processing Flow . 62 Figure 23 VLAN Acceptance Filter . 101 Figure 24 Basic QoS Classification Flow Chart . 103 Figure 25 Basic DP Classification Flow Chart . 104 Figure 26 Basic DSCP Classification Flow Chart . 105 Figure 27 Basic VLAN Classification Flow Chart . 107 Figure 28 Example of QoS Mappings . 119 Figure 29 VLAN Table Update Engine (TUPE) . 125 Figure 30 Router Model . 131 Figure 31 Unicast Routing Table Overview . 132 Figure 32 Multicast Routing Table Overview . 133 Figure 33 Ingress Router Leg Lookup Flow . 134 Figure 34 Ingress Router Leg MAC Address Matching for Unicast Packets . 134 Figure 35 IP Unicast Routing Example . 137 Figure 36 ARP Pointer Remapping . 139 Figure 37 IP Multicast Routing Example . 141 Figure 38 MAC Table Organization . 166 Figure 39 DMAC Lookup . 174 Figure 40 Source Check . 176 Figure 41 PGID Layout . 181 Figure 42 PGID Lookup Decision Forwarding . 182 Figure 43 GLAG Port of Exit Calculation . 184 Figure 44 Port Mask Operation . 185 Figure 45 Policer Hierarchy . 187 Figure 46 Sticky Events Available as Global Events . 195 Figure 47 Port Statistics Counters . 195 Figure 48 Queue Statistics . 197 Figure 49 BUM Policer Statistics . 198 Figure 50 ACL Policer Statistics . 199 Figure 51 Ingress and Egress Routing Statistics per Router Leg per IP Version . 200 Figure 52 sFlow Stamp Format in FCS . 202 Figure 53 Ingress Mirroring in Specific VLAN . 204 Figure 54 Shared Queue System Block Diagram . 205 VMDS-10447 VSC7415 Datasheet Revision 4.1 x Document Outline 1 Revision History 1.1 Revision 4.1 1.2 Revision 4.0 2 Product Overview 2.1 General Features 2.1.1 Layer 2 and Layer 3 Forwarding 2.1.2 Timing and Synchronization 2.1.3 Quality of Service 2.1.4 Security 2.1.5 Management 2.1.6 Product Parameters 2.2 Applications 2.2.1 Wireless Backhaul 2.2.2 Small Cell Application 3 Functional Descriptions 3.1 Register Notations 3.2 Functional Overview 3.2.1 Frame Arrival in Ports and Port Modules 3.2.2 Basic Classification 3.2.3 Security and Control Protocol Classification 3.2.4 Policing 3.2.5 Layer 2 Forwarding 3.2.6 Layer 3 Forwarding 3.2.7 Shared Queue System and Hierarchical Scheduler 3.2.8 Rewriter and Frame Departure 3.2.9 CPU Port Module 3.2.10 Synchronous Ethernet and Precision Time Protocol (PTP) 3.2.11 CPU Subsystem 3.3 Frame Headers 3.3.1 Internal Frame Header Placement 3.3.2 Internal Frame Header Layout 3.3.3 VStaX Header 3.4 Port Numbering and Mappings 3.4.1 Supported SerDes Interfaces 3.4.2 Dual-Media Mode 3.4.3 Logical Port Numbers 3.5 SERDES1G 3.6 SERDES6G 3.7 Copper Transceivers 3.7.1 Register Access 3.7.2 Cat5 Twisted Pair Media Interface 3.7.3 Wake-On-LAN and SecureOn 3.7.4 Ethernet Inline Powered Devices 3.7.5 IEEE 802.3af PoE Support 3.7.6 ActiPHY™ Power Management 3.7.7 Testing Features 3.7.8 VeriPHY™ Cable Diagnostics 3.8 DEV1G and DEV2G5 Port Modules 3.8.1 MAC 3.8.2 Half-Duplex Mode 3.8.3 Physical Coding Sublayer (PCS) 3.8.4 Port Statistics 3.9 Assembler 3.9.1 Setting Up a Port in the Assembler 3.9.2 Setting Up a Port for Frame Injection 3.9.3 Setting Up MAC Control Sublayer PAUSE Frame Detection 3.9.4 Setting Up PFC 3.9.5 Setting Up Assembler Port Statistics 3.9.6 Setting Up the Loopback Path 3.10 Versatile Content-Aware Processor (VCAP) 3.10.1 Configuring VCAP 3.10.2 Wide VCAP Entries and Actions 3.10.3 Individual VCAPs 3.10.4 VCAP Programming Examples 3.11 Pipeline Points 3.11.1 Pipeline Definitions 3.12 Analyzer 3.12.1 Initializing the Analyzer 3.13 VCAP CLM Keys and Actions 3.13.1 Keys Overview 3.13.2 VCAP CLM X1 Key Details 3.13.3 VCAP CLM X2 Key Details 3.13.4 VCAP CLM X4 Key Details 3.13.5 VCAP CLM X8 Key Details 3.13.6 VCAP CLM X16 Key Details 3.13.7 VCAP CLM Actions 3.14 Analyzer Classifier 3.14.1 Basic Classifier 3.14.2 VCAP CLM Processing 3.14.3 QoS Mapping Table 3.14.4 Analyzer Classifier Diagnostics 3.15 VLAN and MSTP 3.15.1 Private VLAN 3.15.2 VLAN Pseudo Code 3.16 VCAP LPM: Keys and Action 3.16.1 VCAP LPM SGL_IP4 Key Details 3.16.2 VCAP LPM DBL_IP4 Key Details 3.16.3 VCAP LPM SGL_IP6 Key Details 3.16.4 VCAP LPM DBL_IP6 Key Details 3.16.5 VCAP LPM Actions 3.17 IP Processing 3.17.1 IP Source/Destination Guard 3.17.2 IP Routing 3.17.3 Statistics 3.17.4 IGMP/MLD Snooping Switch 3.18 VCAP IS2 Keys and Actions 3.18.1 VCAP IS2 Keys 3.18.2 VCAP IS2 Actions 3.19 Analyzer Access Control Lists 3.19.1 VCAP IS2 3.19.2 Analyzer Access Control List Frame Rewriting 3.20 Analyzer Layer 2 Forwarding and Learning 3.20.1 Analyzer MAC Table 3.20.2 MAC Table Updates 3.20.3 CPU Access to MAC Table 3.20.4 SCAN Command 3.20.5 Forwarding Lookups 3.20.6 Source Check and Automated Learning 3.20.7 Automated Aging (AUTOAGE) 3.20.8 Interrupt Handling 3.21 Analyzer Access Control Forwarding, Policing, and Statistics 3.21.1 Mask Handling 3.21.2 Policing 3.21.3 Analyzer Statistics 3.21.4 Analyzer sFlow Sampling 3.21.5 Mirroring 3.22 Shared Queue System and Hierarchical Scheduler 3.22.1 Analyzer Result 3.22.2 Buffer Control 3.22.3 Forwarding 3.22.4 Congestion Control 3.22.5 Queue Mapping 3.22.6 Queue Congestion Control 3.22.7 Scheduling 3.22.8 Queue System Initialization 3.22.9 Miscellaneous Features 3.23 Automatic Frame Injector 3.23.1 Injection Tables 3.23.2 Frame Table 3.23.3 Delay Triggered Injection 3.23.4 Timer Triggered Injection 3.23.5 Injection Queues 3.23.6 Adding Injection Frame 3.23.7 Starting Injection 3.23.8 Stopping Injection 3.23.9 Removing Injection Frames 3.23.10 Port Parameters 3.24 Rewriter 3.24.1 Rewriter Operation 3.24.2 Supported Ports 3.24.3 Supported Frame Formats 3.24.4 Rewriter Initialization 3.24.5 VCAP_ES0 Lookup 3.24.6 Mapping Tables 3.24.7 VLAN Editing 3.24.8 DSCP Remarking 3.24.9 VStaX Header Insertion 3.24.10 Forwarding to GCPU 3.24.11 Layer 3 Routing 3.24.12 Mirror Frames 3.24.13 Internal Frame Header Insertion 3.24.14 Frame Injection from Internal CPU 3.25 Disassembler 3.25.1 Setting Up Ports 3.25.2 Maintaining the Cell Buffer 3.25.3 Setting Up MAC Control Sublayer PAUSE Function 3.25.4 Setting up Flow Control in Half-Duplex Mode 3.25.5 Setting Up Frame Aging 3.25.6 Setting Up Transmit Data Rate Limiting 3.25.7 Error Detection 3.26 Layer 1 Timing 3.27 Hardware Time Stamping 3.27.1 One-Step Functions 3.27.2 Calculation Overview 3.27.3 Detecting Calculation Issues 3.27.4 Two-Step Functions 3.27.5 Time of Day Time Stamping 3.27.6 Time of Day Generation 3.27.7 Multiple PTP Time Domains 3.27.8 Register Interface to 1588 Functions 3.27.9 Configuring I/O Delays 3.28 SyncE and PTP DPLL Timing 3.28.1 Input Clock Selection 3.29 EEC/PEC Controller 3.29.1 Input Qualification Timers 3.29.2 Reference Clock Selection 3.29.3 Output Clock Synthesizers 3.29.4 Synchronizing IEEE 1588 Time Stamping 3.29.5 I/O Pin Mapping 3.30 VRAP Engine 3.30.1 VRAP Request Frame Format 3.30.2 VRAP Response Frame Format 3.30.3 VRAP Header Format 3.30.4 VRAP READ Command 3.30.5 VRAP READ-MODIFY-WRITE Command 3.30.6 VRAP IDLE Command 3.30.7 VRAP PAUSE Command 3.31 Energy Efficient Ethernet 3.32 CPU Injection and Extraction 3.32.1 Frame Injection 3.32.2 Frame Extraction 3.32.3 Forwarding to CPU 3.32.4 Automatic Frame Injection (AFI) 3.33 Priority-Based Flow Control (PFC) 3.33.1 PFC Pause Frame Generation 3.33.2 PFC Frame Reception 3.34 Protection Switching 3.34.1 Ethernet Ring Protection Switching 3.34.2 Link Aggregation 3.34.3 Port Protection Switching 3.35 Low Power Mode 3.35.1 One-Time Configurations for Low Power Mode 3.35.2 General Considerations in Low Power Mode 3.36 Clocking and Reset 3.36.1 Pin Strapping 4 VCore-III System and CPU Interfaces 4.1 VCore-III Configurations 4.2 Clocking and Reset 4.2.1 Watchdog Timer 4.3 Shared Bus 4.3.1 VCore-III Shared Bus Arbitration 4.3.2 Chip Register Region 4.3.3 SI Flash Region 4.3.4 DDR3/DDR3L Region 4.3.5 PCIe Region 4.4 VCore-III CPU 4.4.1 Little Endian and Big Endian Support 4.4.2 Software Debug and Development 4.5 External CPU Support 4.5.1 Register Access and Multimaster Systems 4.5.2 Serial Interface in Slave Mode 4.5.3 MIIM Interface in Slave Mode 4.5.4 Access to the VCore Shared Bus 4.5.5 Mailbox and Semaphores 4.6 PCIe Endpoint Controller 4.6.1 Accessing Endpoint Registers 4.6.2 Enabling the Endpoint 4.6.3 Base Address Registers Inbound Requests 4.6.4 Outbound Interrupts 4.6.5 Outbound Access 4.6.6 Power Management 4.6.7 Device Reset Using PCIe 4.7 Frame DMA 4.7.1 DMA Control Block Structures 4.7.2 Enabling and Disabling FDMA Channels 4.7.3 Channel Counters 4.7.4 FDMA Events and Interrupts 4.7.5 FDMA Extraction 4.7.6 FDMA Injection 4.7.7 Manual Mode 4.8 VCore-III System Peripherals 4.8.1 SI Boot Controller 4.8.2 SI Master Controller 4.8.3 DDR3/DDR3L Memory Controller 4.8.4 Timers 4.8.5 UARTs 4.8.6 Two-Wire Serial Interface 4.8.7 MII Management Controller 4.8.8 GPIO Controller 4.8.9 Serial GPIO Controller 4.8.10 Fan Controller 4.8.11 Temperature Sensor 4.8.12 Memory Integrity Monitor 4.8.13 Interrupt Controller 5 Registers 6 Electrical Specifications 6.1 DC Characteristics 6.1.1 Reference Clock 6.1.2 PLL Clock Output 6.1.3 DPLL Clocks 6.1.4 DDR3/DDR3L SDRAM Interface 6.1.5 SERDES1G 6.1.6 SERDES6G 6.1.7 GPIO, SI, JTAG, and Miscellaneous Signals 6.1.8 Thermal Diode 6.2 AC Characteristics 6.2.1 Reference Clock 6.2.2 PLL Clock Outputs 6.2.3 DPLL Clocks 6.2.4 Jitter Transfer 6.2.5 SERDES1G 6.2.6 SERDES6G 6.2.7 Reset Timing 6.2.8 MII Management 6.2.9 Serial Interface (SI) Boot Master Mode 6.2.10 Serial Interface (SI) Master Mode 6.2.11 Serial Interface (SI) for Slave Mode 6.2.12 DDR SDRAM Interface 6.2.13 JTAG Interface 6.2.14 Serial Inputs/Outputs 6.2.15 Recovered Clock Outputs 6.2.16 Two-Wire Serial Interface 6.2.17 IEEE 1588 Time Tick Outputs 6.3 Current and Power Consumption 6.3.1 Current Consumption 6.3.2 Power Consumption 6.3.3 Power Supply Sequencing 6.4 Operating Conditions 6.5 Stress Ratings 7 Pin Descriptions 7.1 Pin Diagram 7.2 Pins by Function 7.2.1 DDR SDRAM Interface 7.2.2 DPLL Clock 7.2.3 General-Purpose Inputs and Outputs 7.2.4 JTAG Interface 7.2.5 MII Management Interface 7.2.6 Miscellaneous 7.2.7 PCI Express Interface 7.2.8 Power Supplies and Ground 7.2.9 SERDES1G 7.2.10 SERDES6G 7.2.11 Serial CPU Interface 7.2.12 System Clock Interface 7.2.13 Twisted Pair Interface 7.3 Pins by Number 7.4 Pins by Name 8 Package Information 8.1 Package Drawing 8.2 Thermal Specifications 8.3 Moisture Sensitivity 9 Design Guidelines 9.1 Power Supplies 9.2 Power Supply Decoupling 9.2.1 Reference Clock 9.2.2 Single-Ended REFCLK Input 9.3 Interfaces 9.3.1 General Recommendations 9.3.2 SerDes Interfaces (SGMII, 2.5G) 9.3.3 Serial Interface 9.3.4 PCI Express Interface 9.3.5 Two-Wire Serial Interface 9.3.6 DDR3 SDRAM Interface 9.3.7 Thermal Diode External Connection 10 Design Considerations 11 Ordering Information
