Datasheet ADP1032 (Analog Devices) - 5

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Data Sheet ADP1032 Parameter Symbol Min Typ Max Unit Test Conditions/Comments
BUCK REGULATOR Output Voltage VOUT2 5.15 V ADP1032ACPZ-1 5.0 V ADP1032ACPZ-2 and ADP1032ACPZ-4 3.3 V ADP1032ACPZ-3 and ADP1032ACPZ-5 Output Voltage Accuracy −1.5 +1.5 % IOUT2 = 10 mA, applies to al models Load Regulation (ΔVOUT2/VOUT2)/ −0.0005 %/mA IOUT2 = 2 mA to 50 mA ΔIOUT2 Line Regulation (ΔVOUT2/VOUT2)/ 0.0004 %/V VOUT1 = 6 V to 28 V, IOUT2 = 7 mA ΔVOUT1 Power FET On Resistance RON_NFET (BUCK) 1 Ω SW2 current (ISW2) = 100 mA RON_PFET (BUCK) 2.5 Ω ISW2 = 100 mA Current-Limit Threshold ILIM (BUCK) 280 300 320 mA SW2 Leakage Current P Type Metal-Oxide 0.03 0.5 µA VSW2 = 0 V Semiconductor (PMOS) N Type Metal-Oxide 0.03 0.5 µA VSW2 = 28 V Semiconductor (NMOS) Switching Frequency fSW (BUCK) 117.5 125 132.5 kHz SYNC = low or high fSYNC/4 kHz SYNC = external clock Minimum On Time 200 ns Soft Start Timer tSS (BUCK) 8 ms Active Pull-Down Resistor RPD (BUCK) 1.7 kΩ 1.23 V < VOUT1 < 4.5 V ISOLATORS, DC SPECIFICATIONS MCK, MSS, MO, SO, MGPI1, MGPI2, SGPI3 Input Threshold Logic High V 2 IH 0.7 × VxVDD V Logic Low V 2 IL 0.3 × VxVDD V Input Current I 2 I −1 +1 µA 0 V ≤ VINPUT ≤ VxVDD SCK, SSS, SI, MI Output Voltage Logic High V 2 3 4 OH VxVDD − 0.1 V IOx = −20 µA, VIx = VIXH V 2 3 4 xVDD − 0.4 V IOx = −2 mA, VIx = VIXH Logic Low V 3 5 OL 0.1 V IOx = 20 µA, VIx = VIXL 0.15 0.4 V I 3 5 Ox = 2 mA, VIx = VIXL SGPO1, SGPO2, MGPO3 Output Voltage Logic High V 2 3 4 OH VxVDD − 0.1 V IOx = −20 µA, VIx = VIXH V 2 3 4 xVDD − 0.4 V IOx = −500 µA, VIx = VIXH Logic Low V 3 5 OL 0.1 V IOx = 20 µA, VIx = VIXL 0.15 0.4 V I 3 5 Ox = 500 µA, VIx = VIXL SCK, SI, MI Tristate Leakage −1 +0.01 +1 µA MSS = logic high −1 +0.01 +1 µA V 6 2 OX = VxVDD ISOLATORS, SWITCHING SPECIFICATION MCK, MSS, MO, SO SPI Clock Rate SPIMCK 16.6 MHz Latency (MSS) 100 125 ns Delay from MSS going low to the first data out is valid Input Pulse Width tPW 17 ns Within PWD limit Input Pulse Width Distortion tPWD 0.25 6.5 ns |tPLH − tPHL| Rev. 0 | Page 5 of 37 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT COMPANION PRODUCTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS REGULATORY INFORMATION ELECTROMAGNECTIC COMPATIBILITY INSULATION AND SAFETY RELATED SPECIFICATIONS DIN V VDE 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION FLYBACK REGULATOR Flyback Regulator Operation Power Saving Mode (PSM) Flyback Undervoltage Lockout (UVLO) Flyback Regulator Precision Enable Control Flyback Regulator Soft Start Flyback Slew Rate Control Flyback Regulator Overcurrent Protection Flyback Regulator Overvoltage Protection BUCK REGULATOR Buck Regulator Operation Buck Regulator UVLO Buck Regulator Soft Start Buck Regulator Current-Limit Protection Buck Regulator Active Pull-Down Resistor Buck Regulator OVP POWER GOOD POWER-UP SEQUENCE OSCILLATOR AND SYNCHRONIZATION THERMAL SHUTDOWN DATA ISOLATION High Speed SPI Channels GPIO Data Channels APPLICATIONS INFORMATION COMPONENT SELECTION Feedback Resistors Capacitor Selection FLYBACK REGULATOR COMPONENTS SELECTION Input Capacitor Output Capacitor Ripple Current vs. Capacitor Value Schottky Diode Transformer Turn Ratio Primary Inductance Flyback Transformer Saturation Current Series Winding Resistance Leakage Inductance and Clamping Circuits Clamping Resistor Clamping Capacitor Clamping Diode Diode, Zener Diode Clamp Ripple Current (IAC) vs. Inductance Maximum Output Current Calculation BUCK REGULATOR COMPONENTS SELECTION Inductor Output Capacitor INSULATION LIFETIME Surface Tracking Insulation Wear Out Calculation and Use of Parameters Example THERMAL ANALYSIS TYPICAL APPLICATION CIRCUIT PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE