Datasheet ADP1074 (Analog Devices) - 7

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Data Sheet ADP1074 Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FB, OVP, AND PGOOD Overvoltage (OV) threshold for PGOOD 1.3 1.36 1.42 V THRESHOLDS to toggle for FB and OVP pin FB Pin OV Hysteresis 36 mV OVP Pin Hysteresis 36 mV FB Pin UV Threshold Undervoltage (UV) threshold for PGOOD 1.04 1.11 1.16 V to toggle FB Pin UV Hysteresis 36 mV OVP Comparator Delay 320 ns (Includes iCoupler Delay) Time from Fault Condition to OVP pin fault to PGOOD toggling 90 ns PGOOD Toggling FB pin OV/UV to PGOOD toggling 5 μs OVP Pin Leakage Current 1 μA PGOOD Pin Leakage Current 1 μA  OVP Hiccup Time in OVP before entering OVP hiccup 200 μs mode Hiccup time triggered by OVP event 200 ms  1 Short-circuit duration less than 1 μs. Average power must conform to the limit shown in the Absolute Maximum Ratings section.
INSULATION AND SAFETY RELATED SPECIFICATIONS Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
WIDE BODY SOIC iCoupler Rated Dielectric Insulation 1 minute duration 5 kV Voltage Minimum External Air Gap Measured from input terminals to output terminals, 7.6 mm (Clearance) shortest distance through air Minimum External Air Gap Measured from input terminals to output terminals, 7.6 mm (Creepage) shortest distance path along body Minimum Internal Gap (Internal Insulation distance through insulation 0.030 mm Clearance) Tracking Resistance CTI >400 V (Comparative Tracking Index) Isolation Group Material Group II (DIN VDE 0110, 1/89, Table 1) LAND GRID ARRAY (LGA) iCoupler Rated Dielectric Insulation 1 minute duration 2.5 kV Voltage Minimum External Air Gap Measured from input terminals to output terminals, 4 mm (Clearance) shortest distance through air Minimum External Air Gap Measured from input terminals to output terminals, 4 mm (Creepage) shortest distance path along body Minimum Internal Gap (Internal Insulation distance through insulation 0.030 mm Clearance) Tracking Resistance CTI >400 V (Comparative Tracking Index) Isolation Group Material Group I (DIN VDE 0110, 1/89, Table 1) Rev. C | Page 7 of 32 Document Outline FEATURES APPLICATIONS SIMPLIFIED BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS INSULATION AND SAFETY RELATED SPECIFICATIONS REGULATORY INFORMATION DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION DETAILED BLOCK DIAGRAM PRIMARY SIDE SUPPLY, INPUT VOLTAGE, AND LDO SECONDARY SIDE SUPPLY AND LDO PRECISION ENABLE SOFT START PROCEDURE OUTPUT VOLTAGE SENSING AND FEEDBACK LOOP COMPENSATION AND STEADY STATE OPERATION SLOPE COMPENSATION INPUT/OUTPUT CURRENT-LIMIT PROTECTION TEMPERATURE SENSING FREQUENCY SETTING (RT PIN) MAXIMUM DUTY CYCLE FREQUENCY SYNCHRONIZATION SYNCHRONOUS RECTIFIER (SR) DRIVERS OUTPUT OVERVOLTAGE PROTECTION (OVP) ACTIVE CLAMP (PGATE) LEADING EDGE BLANKING GATE DELAY AND SR DEAD TIME LIGHT LOAD MODE (LLM) AND SR PHASE IN EXTERNAL START-UP CIRCUIT SOFT STOP POWER GOOD OCP/FEEDBACK RECOVERY OUTPUT VOLTAGE TRACKING REMOTE SYSTEM RESET OCP COUNTER INSULATION LIFETIME LAYOUT GUIDELINES TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE NOTES